Device Configuration User Guide Agilex™ 3 FPGAs and SoCs

ID 847422
Date 5/23/2025
Public
Document Table of Contents

2.5.3.4. Specifying Pins for Partial Reconfiguration (PR)

The partial reconfiguration signals use GPIO pins.

The following signals control partial reconfiguration in Agilex™ 3 devices:

  • PR_REQUEST
  • PR_READY
  • PR_ERROR
  • PR_DONE

Connect these partial reconfiguration signals to the Partial Reconfiguration External Configuration Controller IP.