Device Configuration User Guide Agilex™ 3 FPGAs and SoCs

ID 847422
Date 5/23/2025
Public
Document Table of Contents

1.1.1. Configuration and Related Signals

The following figure shows the configuration interfaces and configuration-related device functions. Pins shown in dark blue use dedicated SDM I/Os. Pins shown in black use general purpose I/Os (GPIOs). Pins shown in red are dedicated JTAG I/Os.

Figure 1.  Agilex™ 3 Configuration Interfaces

This user guide discusses most of the interfaces shown in the figure. Refer to the separate Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 3 FPGAs and SoCs and Power Management User Guide: Agilex™ 3 FPGAs and SoCs for more information about those features.