Device Configuration User Guide Agilex™ 3 FPGAs and SoCs
ID
847422
Date
5/23/2025
Public
1. Device Configuration User Guide: Agilex™ 3 FPGAs and SoCs
2. Agilex™ 3 Configuration Details
3. Agilex™ 3 Configuration Schemes
4. Including the Reset Release IP in Your Design
5. Remote System Update (RSU)
6. Agilex™ 3 Configuration Features
7. Agilex™ 3 Debugging Guide
8. Document Revision History for the Device Configuration User Guide: Agilex™ 3 FPGAs and SoCs
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II IP (PFL II)
3.1.7.1. Functional Description
3.1.7.2. Designing with the Parallel Flash Loader II IP for Avalon-ST Single Device Configuration
3.1.7.3. Generating the Parallel Flash Loader II IP
3.1.7.4. Constraining the Parallel Flash Loader II IP
3.1.7.5. Using the Parallel Flash Loader II IP
3.1.7.6. Supported Flash Memory Devices
3.1.7.3.1. Controlling Avalon-ST Configuration with Parallel Flash Loader II IP
3.1.7.3.2. Mapping Parallel Flash Loader II IP and Flash Address
3.1.7.3.3. Creating a Single Parallel Flash Loader II IP for Programming and Configuration
3.1.7.3.4. Creating Separate Parallel Flash Loader II IP Functions
3.1.7.4.1. Parallel Flash Loader II IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. Parallel Flash Loader II IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. Parallel Flash Loader II IP Recommended Design Constraints for Using CFI Flash
3.1.7.4.4. Parallel Flash Loader II IP Recommended Constraints for Other Input Pins
3.1.7.4.5. Parallel Flash Loader II IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Skew Tolerance Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Agilex™ 3 Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. Configuration File Format Differences
7.5. Understanding SEUs
7.6. Reading the Unique 64-Bit CHIP ID
7.7. Understanding and Troubleshooting Configuration Pin Behavior
7.8. Configuration Debugger Tool
7.9. CRAM Integrity Check Feature
3.2.5.1. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines
You must minimize the skew on the AS_DATA and AS_CLK pins.
Skew delay includes the following elements:
- The delay due to the differences in board traces lengths on the PCB
- The capacitance loading of the flash device
Use the following equations to determine the skew between AS_CLK and AS_DATA:
- Skew(AS_CLK – AS_DATA) > –AS_CLK/2 + Tdo(max) + Tsu
- Skew(AS_CLK – AS_DATA) < AS_CLK/2 + Tdo(min) – Tho
Hence, the allowable range for skew between AS_CLK and AS_DATA is as follows:
–AS_CLK/2 + Tdo(max) + Tsu < Skew(AS_CLK – AS_DATA) < AS_CLK/2 + Tdo(min) – Tho
- Tsu = Data setup time required by the quad SPI flash. Refer to your quad SPI flash datasheet.
- Tho = Data hold time required by the quad SPI flash. Refer to your quad SPI flash datasheet.
- Tdo = AS_DATA[3:0] output delay. Refer to the AS configuration timing specifications in the Agilex™ 3 Device Data Sheet .
- AS_CLK = AS_CLK clock period.
Example to Determine the Skew for 1 GB Quad SPI Flash Devices
Tsu = 1.75 ns
Tho = 2.0 ns
Tdo(max) = 0.6 ns
Tdo(min) = –0.6 ns
AS_CLK = 10 ns (100 MHz)
- Skew(AS_CLK – AS_DATA) > –AS_CLK/2 + Tdo(max) + Tsu
Skew(AS_CLK – AS_DATA) > –10/2 + 0.6 + 1.75
Skew(AS_CLK – AS_DATA) > –2.65 ns
- Skew(AS_CLK – AS_DATA) < AS_CLK/2 + Tdo(min) – Tho
Skew(AS_CLK – AS_DATA) < 10/2 – 0.6 – 2.0
Skew(AS_CLK – AS_DATA) < 2.4 ns
The allowable range for skew between AS_CLK and AS_DATA is –2.65 ns < Skew(AS_CLK – AS_DATA) < 2.4 ns
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