Device Configuration User Guide Agilex™ 3 FPGAs and SoCs

ID 847422
Date 5/23/2025
Public
Document Table of Contents

3.1.5. Avalon-ST Single-Device Configuration

Figure 19. Connections for Avalon-ST x8 Single-Device Configuration
Figure 20. Connections for Avalon-ST x16 Single-Device Configuration

Notes for Figure:

  1. Refer to MSEL Settings for the correct resistor pull-up and pull-down values for all configuration schemes.
  2. The synchronizers shown in all three figures can be internal if the host is an FPGA or CPLD. If the host is a microprocessor, you must use discrete synchronizers.