Device Configuration User Guide Agilex™ 3 FPGAs and SoCs

ID 847422
Date 5/23/2025
Public
Document Table of Contents

3.2.4. AS Configuration Timing Parameters

Figure 41. AS Configuration Serial Output Timing Diagram
Figure 42. AS Configuration Serial Input Timing Diagram
Table 37.  Text_delay as a Function of AS_CLK Frequency
Symbol Configuration Clock Source Frequency Min (ns) Max (ns)
Text_delay Internal Oscillator 115 MHz 0 20
77 MHz 0 20
58 MHz 0 20
25 MHz 0 24
OSC_CLK_1 15 166 MHz 0 13.5
125 Mhz 0 18
100 MHz 0 24
71.5 MHz 0 35
50 MHz 0 24
25 MHz 0 24
Note: For more information about the timing parameters, refer to the Agilex™ 3 Device Datasheet.
15 For Agilex™ 3 devices with speed grade -7, the clock speed for configuration network runs at 200 MHz when using OSC_CLK_1 and only supports AS_CLK at frequencies of 25 MHz, 50 MHz, and 100 MHz.