LVDS Tunneling Protocol and Interface (LTPI) IP User Guide

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ID 844310
Date 11/25/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Configuring and Generating the IP 3. Simulating the IP 4. Validating the IP 5. Troubleshooting and Debugging Issues 6. Appendix A: Functional Description 7. Appendix B: Registers 8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide
1. Overview x
1.1. About the LVDS Tunneling Protocol and Interface (LTPI) IP 1.2. About the Document 1.3. Applicable Applications 1.4. Key Concepts 1.5. IP Design Flow 1.6. Design Considerations/Guidelines
1.1. About the LVDS Tunneling Protocol and Interface (LTPI) IP x
1.1.1. IP Release Information 1.1.2. IP Features 1.1.3. IP High-level Block Diagram 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Core Support Levels 1.1.8. IP Performance and Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Acronyms 1.2.4. Reference Documents and Training
1.4. Key Concepts x
1.4.1. Interface Tunneling Principle 1.4.2. LTPI Tunneling Methodology 1.4.3. Clock Topology 1.4.4. LTPI Frame 1.4.5. System-level Block Diagram 1.4.6. Link Management 1.4.7. Signal Description
1.4.4. LTPI Frame x
1.4.4.1. Link Detect and Link Speed Selection Frames 1.4.4.2. Link Detect Frame 1.4.4.3. Link Speed Frame 1.4.4.4. Advertise, Configure, and Accept Frames 1.4.4.5. Advertise Frames 1.4.4.6. Configure Frame 1.4.4.7. Accept Frame 1.4.4.8. LTPI Operational Frames 1.4.4.9. Default I/O Frame 1.4.4.10. Default Data Frame
1.4.6. Link Management x
1.4.6.1. Link Training 1.4.6.2. Link Configuration 1.4.6.3. Operational Mode
1.4.7. Signal Description x
1.4.7.1. Clock and Power Signals 1.4.7.2. Channel Signals 1.4.7.3. Avalon® Memory-Mapped Primary Interface Signals 1.4.7.4. Avalon® Memory-Mapped Secondary Interface Signals 1.4.7.5. Avalon® Memory-Mapped CSR Interface Signals 1.4.7.6. Miscellaneous Interface Signals
2. Configuring and Generating the IP x
2.1. Configuring the Quartus® Prime Project 2.2. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP 2.3. Generating HDL for Synthesis and Simulation 2.4. Generating the Simulation Design Example
2.2. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP x
2.2.1. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP Parameters
2.3. Generating HDL for Synthesis and Simulation x
2.3.1. Quartus® Prime Pro Edition Generated File Structure 2.3.2. Quartus® Prime Standard Edition Generated File Structure
2.4. Generating the Simulation Design Example x
2.4.1. Generated Directory Structure and Files
3. Simulating the IP x
3.1. Design Example Features 3.2. Design Example Components 3.3. Configuring the Design Example Parameters 3.4. Simulating the Design Example
3.4. Simulating the Design Example x
3.4.1. Simulation Testbench Flow 3.4.2. Simulation Output
4. Validating the IP x
4.1. Validating the IP Using Agilex™ 5 Device
4.1. Validating the IP Using Agilex™ 5 Device x
4.1.1. Compiling the Design Example in Hardware on Agilex™ 5 Device 4.1.2. Validating the Design Example in Hardware on Agilex™ 5 Device
4.1.2. Validating the Design Example in Hardware on Agilex™ 5 Device x
4.1.2.1. Configuring the Clocks in Hardware 4.1.2.2. Programming the FPGA 4.1.2.3. Running the Hardware Test
6. Appendix A: Functional Description x
6.1. GPIO Channel 6.2. I2C Channel 6.3. UART Channel 6.4. Data Channel 6.5. OEM Channel
1. Overview
2. Configuring and Generating the IP
3. Simulating the IP
4. Validating the IP
5. Troubleshooting and Debugging Issues
6. Appendix A: Functional Description
7. Appendix B: Registers
8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide

1.1.8. IP Performance and Resource Utilization

The LVDS Tunneling Protocol and Interface (LTPI) IP resource utilization values are obtained from the Quartus® Prime Pro Edition software version 25.1.1 for Agilex™ 3 and Agilex™ 5 devices, and Quartus® Prime Standard Edition software version 25.1 for MAX® 10 devices.
Table 6.   LVDS Tunneling Protocol and Interface (LTPI) IP Resource Utilization for Agilex™ 3 and Agilex™ 5 Devices
LVDS Tunneling Protocol and Interface (LTPI) IP Configuration Setting Combination ALUTs Dedicated Logic Registers Block Memory Bits
Fixed Configuration Variable Configuration
  • Number of NL GPIO Interface: 16
  • Number of LL GPIO Interface: 16
  • Number of UART Bus Interface: 2
  • Number of I2C Bus Interface: 6
  • Data Channel MailBox Enable: Enable
  • OEM Data Width: 32
  • UART Baud Rate: 9600
  • I2C Bus Speed Mode: STANDARD (100KHz)
  • Device Type: Controller
  • CSR Lite: Disable
 5,961 5,674 3,584
  • Device Type: Controller
  • CSR Lite: Enable
 4,176 4,271 3,520
  • Device Type: Target
  • CSR Lite: Disable
 5,889 5,368 3,408
  • Device Type: Target
  • CSR Lite: Enable
 4,121 3,976 3,344
Table 7.   LVDS Tunneling Protocol and Interface (LTPI) IP Resource Utilization for MAX® 10 Devices
LVDS Tunneling Protocol and Interface (LTPI) IP Configuration Setting Combination ALUTs Dedicated Logic Registers Block Memory Bits
Fixed Configuration Variable Configuration
  • Number of NL GPIO Interface: 16
  • Number of LL GPIO Interface: 16
  • Number of UART Bus Interface: 2
  • Number of I2C Bus Interface: 6
  • Data Channel MailBox Enable: Enable
  • OEM Data Width: 32
  • UART Baud Rate: 9600
  • I2C Bus Speed Mode: STANDARD (100KHz)
  • Device Type: Controller
  • CSR Lite: Disable
 9,582 5,108 3,728
  • Device Type: Controller
  • CSR Lite: Enable
 7,699 4,068 3,728
  • Device Type: Target
  • CSR Lite: Disable
 9,251 4,720 3,680
  • Device Type: Target
  • CSR Lite: Enable
 7,405 3,688 3,680
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