LVDS Tunneling Protocol and Interface (LTPI) IP User Guide

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ID 844310
Date 11/25/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Configuring and Generating the IP 3. Simulating the IP 4. Validating the IP 5. Troubleshooting and Debugging Issues 6. Appendix A: Functional Description 7. Appendix B: Registers 8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide
1. Overview x
1.1. About the LVDS Tunneling Protocol and Interface (LTPI) IP 1.2. About the Document 1.3. Applicable Applications 1.4. Key Concepts 1.5. IP Design Flow 1.6. Design Considerations/Guidelines
1.1. About the LVDS Tunneling Protocol and Interface (LTPI) IP x
1.1.1. IP Release Information 1.1.2. IP Features 1.1.3. IP High-level Block Diagram 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Core Support Levels 1.1.8. IP Performance and Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Acronyms 1.2.4. Reference Documents and Training
1.4. Key Concepts x
1.4.1. Interface Tunneling Principle 1.4.2. LTPI Tunneling Methodology 1.4.3. Clock Topology 1.4.4. LTPI Frame 1.4.5. System-level Block Diagram 1.4.6. Link Management 1.4.7. Signal Description
1.4.4. LTPI Frame x
1.4.4.1. Link Detect and Link Speed Selection Frames 1.4.4.2. Link Detect Frame 1.4.4.3. Link Speed Frame 1.4.4.4. Advertise, Configure, and Accept Frames 1.4.4.5. Advertise Frames 1.4.4.6. Configure Frame 1.4.4.7. Accept Frame 1.4.4.8. LTPI Operational Frames 1.4.4.9. Default I/O Frame 1.4.4.10. Default Data Frame
1.4.6. Link Management x
1.4.6.1. Link Training 1.4.6.2. Link Configuration 1.4.6.3. Operational Mode
1.4.7. Signal Description x
1.4.7.1. Clock and Power Signals 1.4.7.2. Channel Signals 1.4.7.3. Avalon® Memory-Mapped Primary Interface Signals 1.4.7.4. Avalon® Memory-Mapped Secondary Interface Signals 1.4.7.5. Avalon® Memory-Mapped CSR Interface Signals 1.4.7.6. Miscellaneous Interface Signals
2. Configuring and Generating the IP x
2.1. Configuring the Quartus® Prime Project 2.2. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP 2.3. Generating HDL for Synthesis and Simulation 2.4. Generating the Simulation Design Example
2.2. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP x
2.2.1. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP Parameters
2.3. Generating HDL for Synthesis and Simulation x
2.3.1. Quartus® Prime Pro Edition Generated File Structure 2.3.2. Quartus® Prime Standard Edition Generated File Structure
2.4. Generating the Simulation Design Example x
2.4.1. Generated Directory Structure and Files
3. Simulating the IP x
3.1. Design Example Features 3.2. Design Example Components 3.3. Configuring the Design Example Parameters 3.4. Simulating the Design Example
3.4. Simulating the Design Example x
3.4.1. Simulation Testbench Flow 3.4.2. Simulation Output
4. Validating the IP x
4.1. Validating the IP Using Agilex™ 5 Device
4.1. Validating the IP Using Agilex™ 5 Device x
4.1.1. Compiling the Design Example in Hardware on Agilex™ 5 Device 4.1.2. Validating the Design Example in Hardware on Agilex™ 5 Device
4.1.2. Validating the Design Example in Hardware on Agilex™ 5 Device x
4.1.2.1. Configuring the Clocks in Hardware 4.1.2.2. Programming the FPGA 4.1.2.3. Running the Hardware Test
6. Appendix A: Functional Description x
6.1. GPIO Channel 6.2. I2C Channel 6.3. UART Channel 6.4. Data Channel 6.5. OEM Channel
1. Overview
2. Configuring and Generating the IP
3. Simulating the IP
4. Validating the IP
5. Troubleshooting and Debugging Issues
6. Appendix A: Functional Description
7. Appendix B: Registers
8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide

8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide

Document Version Quartus® Prime Version IP Version Changes
2025.11.25 25.1std 25.1
  • Retitled document to LVDS Tunneling Protocol and Interface (LTPI) IP User Guide.
  • Added support for MAX® 10 FPGAs in the following topics:
    • IP Release Information
    • Device Family Support
    • Device Speed Grade Suppport
    • IP Core Support Levels
    • IP Performance and Resource Utilization
    • Generated Directory Structure and Files
    • Simulating the Design Example
  • Added Licensing the IP.
  • Updated information about PLL dynamic reconfiguration in Design Considerations/Guidelines.
  • Updated mentions of Quartus® Prime Pro Edition to Quartus® Prime for broader applicability and where applicable. The LVDS Tunneling Protocol and Interface (LTPI) IP now supports MAX® 10 devices available in the Quartus® Prime Standard Edition software.
  • Retitled topic Generated File Structure to Quartus® Prime Pro Edition Generated File Structure.
  • Added new topic— Quartus® Prime Standard Edition Generated File Structure.
2025.08.15 25.1.1 2.0.0
  • Updated IP name "LVDS Tunneling Protocol and Interface" to "LVDS Tunneling Protocol and Interface (LTPI)".
  • Added support for Agilex™ 3 device family.
  • Updated mentions of "CSR Light" to "CSR Lite".
  • Updated Table: LVDS Tunneling Protocol and Interface (LTPI) IP Release Information.
  • Updated Licensing the IP.
  • Added new topic—IP Core Support Levels.
  • Updated mentions of "TDS" to "LVDS" in the document.
  • Removed TDS from Table: Acronym.
  • Removed Table: Supported IPs.
  • Updated Table: Miscellaneous Signals in Miscellaneous Interface Signals:
    • Updated signal name reg_tag_in to tag_in.
    • Updated signal name reg_tag_out to tag_out.
  • Updated Figure: Design Flow in IP Design Flow.
  • Updated Design Considerations/Guidelines.
  • Updated Configuring the Quartus® Prime Pro Edition Project.
  • Removed topic Compiling the Design Example in Hardware under the Configuring and Generating the IP chapter.
  • Updated the figures and tables in Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP Parameters.
  • Corrected the redundant I2C Bus Speed Mode parameter to Number of I2C Bus Interface in Table: LVDS Tunneling Protocol and Interface IP Parameters—Channel Settings Tab.
  • Updated Design Example Components.
  • Updated list of supported simulators in Simulating the Design Example.
  • Added Agilex™ 5 hardware design example information in the following topics:
    • Configuring the Design Example Parameters
    • Validating the IP
  • Added the following table information in Appendix B: Registers:
    • Table: Types of Register Access
    • Table: LTPI Control and Status Registers
2025.02.24 24.3.1 1.0.0 Initial release.
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