LVDS Tunneling Protocol and Interface (LTPI) IP User Guide

Download PDF
ID 844310
Date 11/25/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Configuring and Generating the IP 3. Simulating the IP 4. Validating the IP 5. Troubleshooting and Debugging Issues 6. Appendix A: Functional Description 7. Appendix B: Registers 8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide
1. Overview x
1.1. About the LVDS Tunneling Protocol and Interface (LTPI) IP 1.2. About the Document 1.3. Applicable Applications 1.4. Key Concepts 1.5. IP Design Flow 1.6. Design Considerations/Guidelines
1.1. About the LVDS Tunneling Protocol and Interface (LTPI) IP x
1.1.1. IP Release Information 1.1.2. IP Features 1.1.3. IP High-level Block Diagram 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Core Support Levels 1.1.8. IP Performance and Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Acronyms 1.2.4. Reference Documents and Training
1.4. Key Concepts x
1.4.1. Interface Tunneling Principle 1.4.2. LTPI Tunneling Methodology 1.4.3. Clock Topology 1.4.4. LTPI Frame 1.4.5. System-level Block Diagram 1.4.6. Link Management 1.4.7. Signal Description
1.4.4. LTPI Frame x
1.4.4.1. Link Detect and Link Speed Selection Frames 1.4.4.2. Link Detect Frame 1.4.4.3. Link Speed Frame 1.4.4.4. Advertise, Configure, and Accept Frames 1.4.4.5. Advertise Frames 1.4.4.6. Configure Frame 1.4.4.7. Accept Frame 1.4.4.8. LTPI Operational Frames 1.4.4.9. Default I/O Frame 1.4.4.10. Default Data Frame
1.4.6. Link Management x
1.4.6.1. Link Training 1.4.6.2. Link Configuration 1.4.6.3. Operational Mode
1.4.7. Signal Description x
1.4.7.1. Clock and Power Signals 1.4.7.2. Channel Signals 1.4.7.3. Avalon® Memory-Mapped Primary Interface Signals 1.4.7.4. Avalon® Memory-Mapped Secondary Interface Signals 1.4.7.5. Avalon® Memory-Mapped CSR Interface Signals 1.4.7.6. Miscellaneous Interface Signals
2. Configuring and Generating the IP x
2.1. Configuring the Quartus® Prime Project 2.2. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP 2.3. Generating HDL for Synthesis and Simulation 2.4. Generating the Simulation Design Example
2.2. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP x
2.2.1. Configuring the LVDS Tunneling Protocol and Interface (LTPI) IP Parameters
2.3. Generating HDL for Synthesis and Simulation x
2.3.1. Quartus® Prime Pro Edition Generated File Structure 2.3.2. Quartus® Prime Standard Edition Generated File Structure
2.4. Generating the Simulation Design Example x
2.4.1. Generated Directory Structure and Files
3. Simulating the IP x
3.1. Design Example Features 3.2. Design Example Components 3.3. Configuring the Design Example Parameters 3.4. Simulating the Design Example
3.4. Simulating the Design Example x
3.4.1. Simulation Testbench Flow 3.4.2. Simulation Output
4. Validating the IP x
4.1. Validating the IP Using Agilex™ 5 Device
4.1. Validating the IP Using Agilex™ 5 Device x
4.1.1. Compiling the Design Example in Hardware on Agilex™ 5 Device 4.1.2. Validating the Design Example in Hardware on Agilex™ 5 Device
4.1.2. Validating the Design Example in Hardware on Agilex™ 5 Device x
4.1.2.1. Configuring the Clocks in Hardware 4.1.2.2. Programming the FPGA 4.1.2.3. Running the Hardware Test
6. Appendix A: Functional Description x
6.1. GPIO Channel 6.2. I2C Channel 6.3. UART Channel 6.4. Data Channel 6.5. OEM Channel
1. Overview
2. Configuring and Generating the IP
3. Simulating the IP
4. Validating the IP
5. Troubleshooting and Debugging Issues
6. Appendix A: Functional Description
7. Appendix B: Registers
8. Document Revision History for the LVDS Tunneling Protocol and Interface (LTPI) IP User Guide

7. Appendix B: Registers

Table 52.  Types of Register Access
Access Definition
RO Read only.
RW Read and write.
RWC Read, write and clear. The user application writes 1 to the register bit(s) to invoke a defined instruction. The IP core clears the bit(s) upon executing the instruction.
Table 53.  LTPI Control and Status Registers
Offset Name Bit Field Type Bit Field Definition
0x00 LTPI Link Status 19:16 RO

Local LTPI Link State (SCM)
State Encoding
Link Detect 0x0
Link Speed 0x1
Advertise 0x2
Configuration 0x3
Operational 0x4
Reserved 0x5–0xF
15:12 RO

Remote LTPI Link State (HPM)
State Encoding
Link Detect 0x0
Link Speed 0x1
Advertise 0x2
Configuration 0x3
Operational 0x4
Reserved 0x5–0xF
11:8 RO LTPI Link Speed
Link Speed Encoding
Base Freq x1 0x0
Base Freq x2 0x1
Base Freq x3 0x2
Base Freq x4 0x3
Base Freq x6 0x4
Base Freq x8 0x5
Base Freq x10 0x6
Reserved 0x7–0xF
7 RO
DDR mode:
  • 0: SDR mode
  • 1: DDR mode
6 — Reserved
5 RWC Link Configure/Accept Timeout Error
4 RWC Link Speed Timeout Error
3 RWC Unknown Comma Symbol Error
2 RWC Frame CRC Error
1 RWC LTPI Link Lost Error
0 RO LTPI Link Aligned
  • 0: Link not aligned
  • 1: Link aligned
0x04 LTPI Detect Capabilities Local 31:24 — Reserved
23:8 RW

Link Speed Capabilities

Speed capabilities as in Table 15

(BMC can use the capabilities register to override Link Speed capabilities)
7:4 RO

Local LTPI Major Version

Major version BCD encoded as in Table 16
3:0 RO

Local LTPI Minor Version

Minor version BCD encoded as in Table 16
0x08 LTPI Detect Capabilities Remote 31:24 — Reserved
23:8 RO

Link Speed Capabilities

Speed capabilities as in Table 15
7:4 RO

Remote LTPI Major Version

Major version BCD encoded as in Table 16
3:0 RO

Remote LTPI Minor Version

Minor version BCD encoded as in Table 16
0x0C LTPI Platform ID Local 31:16 — Reserved
15:0 RO

Local LTPI Platform ID

Platform ID supported by Local LTPI as defined in Table 18
0x10 LTPI Platform ID Remote 31:16 — Reserved
15:0 RO

Remote LTPI Platform ID

Platform ID as advertised by Remote LTPI as defined in Table 18
0x14 LTPI Advertise Capabilities Local Low 31:0 RW

Local LTPI Capabilities Low – Bytes 3:0

LTPI Capabilities as defined in Table 20
0x18 LTPI Advertise Capabilities Local High 31:0 RW

Local LTPI Capabilities High – Bytes 7:4

LTPI Capabilities as defined in Table 20
0x1C LTPI Advertise Capabilities Remote Low 31:0 RO

Remote LTPI Capabilities Low – Bytes 3:0

LTPI Capabilities as defined in Table 20
0x20 LTPI Advertise Capabilities Remote High 31:0 RO

Remote LTPI Capabilities High – Bytes 7:4

LTPI Capabilities as defined in Table 20
0x24 LTPI Default Configuration Low 31:0 RO

LTPI Default Configuration Low – Bytes 3:0

LTPI Capabilities as defined in Table 20
0x28 LTPI Default Configuration High 31:0 RO

LTPI Default Configuration Low – Bytes 7:4

LTPI Capabilities as defined in Table 20
0x2C LTPI Link Alignment Error Counter 31:0 RWC LTPI Link Alignment Error Counter
0x30 LTPI Link Lost Error Counter 31:0 RWC LTPI Link Lost Error Counter
0x34 LTPI CRC Error Counter 31:0 RWC LTPI CRC Error Counter
0x38 Unknown Comma Error Counter 31:0 RWC LTPI Unknown Comma Error Counter
0x3C Link Speed Timeout Error Counter 31:0 RWC LTPI Link Speed Timeout Error Counter
0x40 Link Configure/Accept Timeout Error Counter 31:0 RWC LTPI Link Configure/Accept Timeout Error Counter
0x44 Link Training RX Frames Counter Low 31:24 RWC Link Configure/Accept Frames Received Counter
23:16 RWC Link Speed Frames Received Counter
15:0 RWC Link Detect Frames Received Counter
0x48 Link Training RX Frames Counter High 31:0 RWC Link Advertise Frames Received Counter
0x4C Link Training TX Frames Counter Low 31:24 RWC Link Configure/Accept Frames Sent Counter
23:16 RWC Link Speed Frames Sent Counter
15:0 RWC Link Detect Frames Sent Counter
0x50 Link Training TX Frames Counter High 31:0 RWC Link Advertise Frames Sent Counter
0x54 Operational RX Frames Counter 31:0 RWC Operational Frames Received
0x58 Operational TX Frames Counter 31:0 RWC Operational Frames Transmitted
0x5C–0x7F Reserved — — —
0x80 LTPI Link Control 31:12 — Reserved
11 RW Trigger Configuration State
10 RW Automatically Move to Configuration State
9 RW Data Channel Reset
8:2 RW

LTPI I2C Channel Reset

Write I2C Channel Link Number
1 RW LTPI Link Retraining Request
0 RW LTPI Link Software Reset
0x84–0xFF Reserved — — —
Level Two Title