Altera® AXI4 Bus Functional Model User Guides

ID 838773
Date 3/19/2025
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.1.1. Altera® AXI4 Memory-Mapped Specification Support

The AMBA AXI4 memory-mapped protocol supports high-performance, high-frequency system designs for communication between manager and subordinate components. Some of the key features of the protocol are:

  • Separate address, control, and data phases.
  • Burst based transactions using only the start address.
  • Separate read and write data channels.
  • Supports out-of-order transaction completion using transaction IDs.
  • Atomic accesses (locked, exclusive) as well as for QoS, region, and user defined signaling.

For more details on the AXI4 memory-mapped specification, refer to the AMBA web site. For more details on Platform Designer support for AXI4, refer to Quartus® Prime Pro Edition User Guide: Platform Designer.