1. DisplayPort IP Design Example Quick Start Guide
2. DisplayPort IP Design Examples
3. DisplayPort SST Parallel Loopback without PCR Design Example
4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example
5. DisplayPort SST TX-Only Design Example
6. DisplayPort SST RX-Only Design Example
7. Document Revision History for the GTS DisplayPort FPGA IP Design Example User Guide
1.5.1. Compiling and Testing the Design Using Agilex™ 3 FPGA and SoC C-Series Development Kit
1.5.2. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit
1.5.3. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular Development Kit Connector with No FMC Mode
1.5.4. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular Development Kit Connector with Bitec Rev 8 Daughter Card
1. DisplayPort IP Design Example Quick Start Guide
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 25.3 |
| IP Version 21.0.0 |
The DisplayPort IP design example includes a preliminary simulation testbench and a hardware design that supports compilation and hardware testing.
The DisplayPort IP offers the following design examples:
- DisplayPort single stream transport (SST) Parallel Loopback without a Pixel Clock Recovery (PCR) module
- DisplayPort SST Parallel Loopback with AXI4-S Video Interface
- DisplayPort SST RX-Only
- DisplayPort SST TX-Only
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Note: A design example is disabled if the selected IP options are incompatible with it. For example, If the DisplayPort source is enabled, the RX-only design becomes unavailable. Refer to the Table 2 table for the required IP settings.
Figure 1. Development Stages