DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs

Download PDF
ID 823560
Date 8/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort IP Design Example Quick Start Guide 2. DisplayPort IP Design Examples 3. DisplayPort SST Parallel Loopback without PCR Design Example 4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example 5. DisplayPort SST TX-Only Design Example 6. DisplayPort SST RX-Only Design Example 7. Document Revision History for the DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs
1. DisplayPort IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Regenerating the Nios V .elf File 1.7. DisplayPort IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit 1.5.2. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular Development Kit Connector with No FMC Mode 1.5.3. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular Development Kit Connecter with Bitec Rev 8 Daughter Card
2. DisplayPort IP Design Examples x
2.1. Design Components 2.2. DisplayPort IP Design Example Clock Domains 2.3. Interface Signals and Parameters 2.4. Simulation Testbench 2.5. DisplayPort Duplex or Dual Simplex Design Examples
2.5. DisplayPort Duplex or Dual Simplex Design Examples x
2.5.1. DisplayPort Duplex Designs 2.5.2. DisplayPort Dual-Simplex Designs
3. DisplayPort SST Parallel Loopback without PCR Design Example x
3.1. Features 3.2. Functional Description
4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example x
4.1. Features 4.2. Functional Description
5. DisplayPort SST TX-Only Design Example x
5.1. DisplayPort SST TX-Only Features 5.2. DisplayPort SST TX-Only Functional Description
6. DisplayPort SST RX-Only Design Example x
6.1. DisplayPort SST RX-Only Features 6.2. DisplayPort SST RX-Only Functional Description
1. DisplayPort IP Design Example Quick Start Guide
2. DisplayPort IP Design Examples
3. DisplayPort SST Parallel Loopback without PCR Design Example
4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example
5. DisplayPort SST TX-Only Design Example
6. DisplayPort SST RX-Only Design Example
7. Document Revision History for the DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs

1.7. DisplayPort IP Design Example Parameters

The following table lists the DisplayPort IP design example parameters for Agilex™ 5 devices:

Table 2.  DisplayPort IP Design Example Parameters for Agilex™ 5 Devices
Parameter Value Description
Available Design Example
Select Design
  • None
  • 1
  • DisplayPort SST Parallel Loopback without PCR
  • DisplayPort SST Parallel Loopback with AXIS Video Interface
  • DisplayPort RX-only
  • DisplayPort TX-only
 Select the design example to generate.
  • None indicates no design example is available for the current parameter selection.
  • 1 indicates you have invalid parameters on the IP tab.
  • DisplayPort SST Parallel Loopback without PCR demonstrates parallel loopback from DisplayPort sink to DisplayPort source without a Pixel Clock Recovery (PCR) module when you turn on the Enable Video Input Image Port parameter.
  • DisplayPort SST Parallel Loopback with AXIS Video Interface demonstrates parallel loopback from DisplayPort sink to DisplayPort source with AXIS Video interface when you set Enable Active Video Data Protocols to AXIS-VVP Full.
  • DisplayPort RX-only demonstrates an RX-only design. The design example software reports the RX link status.
  • DisplayPort TX-only demonstrates a TX-only design. The Enable Video Input Image Port parameter must be disabled. The design example software reports the TX link status. The design produces color bars in 1080p format.
Transceiver Clock
  • PMA Direct
  • System PLL
 To enable more flexible clocking schemes, you can generate the design example using either the System PLL or the PMA Direct clocking methods.
Design Example Files
Simulation On, Off Turn on to generate the necessary files for the simulation testbench.
Synthesis On, Off Turn on to generate the necessary files for Quartus® Prime compilation and hardware design.
Generated HDL Format
Generate File Format Verilog, VHDL Select your preferred HDL format for the generated design example fileset.
Note: This option only determines the format for the generated top level IP files. All other files (e.g. example testbenches and top level files for hardware demonstration) are in Verilog HDL format.
Target Development Kit
Select Board
  • No Development Kit
  • Agilex™ 5 FPGA E-Series DK A5ED065BB32AE6SR0 Premium Development Kit
  • Custom Development Kit
  • Agilex™ 5 FPGA E-Series DK A5ED065BB32AE6SR0 Modular Development Kit
 Select the board for the targeted design example.
  • No Development Kit excludes all hardware aspects for the design example. The IP sets all pin assignments to virtual pins.
  • Agilex™ 5 FPGA E-Series DK A5ED065BB32AE6SR0 Premium Development Kit: This option automatically sets the project's target device to the A5ED065BB32AE6SR0. You may change the target device using the Change Target Device parameter, but Altera strongly recommends that you do not override the target device. If you require a different device, select the Custom Development Kit option. The IP sets all pin assignments according to the development kit.
  • Custom Development Kit allows the design example to be tested on a third-party development kit with an Intel FPGA. Set the project's target device to match the current project's target device, and modify the pin assignments as necessary.
  • Agilex™ 5 FPGA E-Series DK A5ED065BB32AE6SR0 Modular Development Kit automatically sets the project's target device to the A5ED065BB32AE6SR0. You may change the target device using the Change Target Device parameter, but Altera strongly recommends that you do not override the target device. If you require a different device, select the Custom Development Kit option. The IP sets all pin assignments according to the development kit.
FMC Revision
  • Bitec Rev 8
  • Devkit Connector (No FMC)
  • Parretto Rev 1
 Choose the physical interface location for the DisplayPort connectors:
  • Bitec Rev 8 selects the FMC card from Bitec Revision 8 to provide the DisplayPort connectors.
  • Devkit Connector (No FMC) is only available for the Modular Development Kit and enables the carrier board DisplayPort connectors. No FMC is required to be fitted.
  • Parretto Rev 1 selects the Tentiva FMC card from Parretto. This FMC card supports all DisplayPort rates
Target Device
Change Target Device On, Off Turn on and select the preferred device variant for the development kit.
Level Two Title