Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide

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ID 823179
Date 4/30/2025
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Document Table of Contents
Document Table of Contents x
1. Design Example Description 2. Quick Start Guide 3. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide
1. Design Example Description x
1.1. H2D ST to D2H ST Loopback Design Example
1.1. H2D ST to D2H ST Loopback Design Example x
1.1.1. DMA PCIe* Mode Design Example 1.1.2. DMA SoC Mode Design Example
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Testbench 2.5. Compiling the Design Example 2.6. Hardware and Software Requirements 2.7. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. DMA SoC Mode Example Design 2.3.2. DMA PCIe Mode Example Design
2.3.2. DMA PCIe Mode Example Design x
2.3.2.1. Running Simulation using VCS* MX 2.3.2.2. Running Simulation Using QuestaSim* 2.3.2.3. Running Simulation using Xcelium 2.3.2.4. Running Simulation using Riviera-PRO
2.4. Testbench x
2.4.1. DMA SoC Mode H2D ST to D2H ST Loopback Example Testbench 2.4.2. DMA PCIe Mode H2D ST to D2H ST Loopback & H2D MM Example Testbench
2.4.2. DMA PCIe Mode H2D ST to D2H ST Loopback & H2D MM Example Testbench x
2.4.2.1. Design Example Testbench
2.7. Running the Design Example x
2.7.1. Running the DMA SoC Mode H2D ST to D2H ST Loopback Design Example 2.7.2. Running the DMA PCIe Mode H2D ST to D2H ST Loopback Design Example
2.7.1. Running the DMA SoC Mode H2D ST to D2H ST Loopback Design Example x
2.7.1.1. Building the Software Application Project for Nios® V/m Processor 2.7.1.2. Programming the Example Design into the Development Board
2.7.2. Running the DMA PCIe Mode H2D ST to D2H ST Loopback Design Example x
2.7.2.1. Installing the Linux Kernel Driver 2.7.2.2. Running the Loopback Design Example
2.7.2.2. Running the Loopback Design Example x
2.7.2.2.1. Testing H2D ST to D2H ST Loopback 2.7.2.2.2. Testing H2D MM
1. Design Example Description
2. Quick Start Guide
3. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide

2.7.1.2. Programming the Example Design into the Development Board

To program example design into the FPGA and to run your application, use Quartus® Prime Programmer tool.
  1. Download the .sof file into the board.
  2. Run juart-terminal to print the output of the Nios® V/m processor system.
  3. Download the .elf using the niosv-download <elf file> command 
[niosv-shell] ~ $ juart-terminal
juart-terminal: connected to hardware target using JTAG UART on cable
juart-terminal: "Agilex_5E MDK Carrier on 10.244.216.212 [USB-1]", device 1, instance 0
juart-terminal: (Use the IDE stop button or Ctrl-C to terminate)

INFO: ********************************************************************************
INFO: Altera sSGDMA multiport AXI-ST loopback & AXI4-MM memory access soc-mode example
INFO: ********************************************************************************
INFO: Enabling prefetcher!
INFO: Enable prefetcher: ret 0, enable 1
INFO: Dev csr base: 0x400000. total port 2
INFO: *******************************************************************************
INFO: Streaming Interface -- start loopback transfer for  H2D-ST0-->>>>>>--D2H-ST0 
INFO: *******************************************************************************
INFO: Fill H2D ST ret 0, length 192 bytes
INFO: Fill H2D ST ret 0, length 192 bytes
INFO: Fill H2D ST ret 0, length 192 bytes
INFO: Creating descriptors below for non-contiguous memory transfer => Scatter-Gather operation..!!!
INFO: Fill H2D ST ret 0, length 320 bytes, src_adr mem loc {[start => 0x27560 ~~~ end => 0x2769f]}
INFO: Fill H2D ST ret 0, length 640 bytes, src_adr mem loc {[start => 0x27880 ~~~ end => 0x27aff]}
INFO: Fill H2D ST ret 0, length 480 bytes, src_adr mem loc {[start => 0x276a0 ~~~ end => 0x2787f]}
INFO: H2D_ST update insert ptr ret 0.
INFO: H2D_ST insert ptr ret 0, val 7
INFO: Interrupt D2H_ST before: 0.
INFO: Creating multiple descriptors (maximum payload/data length 96 bytes for each descriptors)..
INFO: Fill D2H ST ret 0, length 576 bytes
INFO: Number of D2H-ST descriptors created for length 576 bytes based on configured MAX_DESC_LENGTH == 6 
INFO: Fill D2H ST ret 0, length 320 bytes, dest_adr mem loc {[start => 0x27d40 ~~~ end => 0x27e7f]}
INFO: Fill D2H ST ret 0, length 640 bytes, dest_adr mem loc {[start => 0x28060 ~~~ end => 0x282df]}
INFO: Fill D2H ST ret 0, length 480 bytes, dest_adr mem loc {[start => 0x27e80 ~~~ end => 0x2805f]}
INFO: D2H_ST update insert ptr ret 0.
INFO: D2H_ST insert ptr ret 0, val 10
INFO: check H2D_ST for complete.
INFO: H2D_ST resp before poll for completion called..
INFO: resp format 0x13, Idx 2, length 192 bytes, status 0x80
INFO: resp format 0x13, Idx 3, length 192 bytes, status 0x80
INFO: resp format 0x13, Idx 4, length 192 bytes, status 0x81
INFO: resp format 0x13, Idx 5, length 320 bytes, status 0x80
INFO: resp format 0x13, Idx 6, length 640 bytes, status 0x80
INFO: resp format 0x13, Idx 7, length 480 bytes, status 0x81
INFO: HW Extract pointer after H2D_ST 7, ret 0
INFO: H2D_ST complete ret 0, last idx 7
INFO: H2D_ST resp after poll for completion called..
INFO: resp format 0x13, Idx 2, length 192 bytes, status 0x0
INFO: resp format 0x13, Idx 3, length 192 bytes, status 0x0
INFO: resp format 0x13, Idx 4, length 192 bytes, status 0x1
INFO: resp format 0x13, Idx 5, length 320 bytes, status 0x0
INFO: resp format 0x13, Idx 6, length 640 bytes, status 0x0
INFO: resp format 0x13, Idx 7, length 480 bytes, status 0x1
INFO: D2H_ST status before interrupt.
INFO: gcsr status: val 0x80000000
INFO: gcsr irq status: val 0x1
INFO: type 0, status: ret 0, val 0x90000014
INFO: interrupt cnt 0, completed desc 0
INFO: D2H_ST resp before interrupt enabled.
INFO: resp format 0x17, Idx 2, length 96 bytes, status 0x80
INFO: resp format 0x17, Idx 3, length 96 bytes, status 0x80
INFO: resp format 0x17, Idx 4, length 96 bytes, status 0x80
INFO: resp format 0x17, Idx 5, length 96 bytes, status 0x80
INFO: resp format 0x17, Idx 6, length 96 bytes, status 0x80
INFO: resp format 0x17, Idx 7, length 96 bytes, status 0x81
INFO: resp format 0x17, Idx 8, length 320 bytes, status 0x80
INFO: resp format 0x17, Idx 9, length 640 bytes, status 0x80
INFO: resp format 0x17, Idx 10, length 480 bytes, status 0x85
INFO: D2H_ST status after interrupt enabled.
INFO: gcsr status: val 0x0
INFO: gcsr irq status: val 0x0
INFO: type 0, status: ret 0, val 0x14
INFO: interrupt cnt 1, completed desc 9
INFO: HW Extract pointer after D2H_ST 10, ret 0
INFO: D2H_ST resp after interrupt.
INFO: resp format 0x17, Idx 2, length 96 bytes, status 0x0
INFO: resp format 0x17, Idx 3, length 96 bytes, status 0x0
INFO: resp format 0x17, Idx 4, length 96 bytes, status 0x0
INFO: resp format 0x17, Idx 5, length 96 bytes, status 0x0
INFO: resp format 0x17, Idx 6, length 96 bytes, status 0x0
INFO: resp format 0x17, Idx 7, length 96 bytes, status 0x1
INFO: resp format 0x17, Idx 8, length 320 bytes, status 0x0
INFO: resp format 0x17, Idx 9, length 640 bytes, status 0x0
INFO: resp format 0x17, Idx 10, length 480 bytes, status 0x5
INFO: Transferred data matches with received data..!!!
INFO: Total streamed transfer length = 2016 bytes
INFO: Free resources!
INFO: Reset Ports!
INFO: Memory copy over DMA sucessfully completed..!!! End of sSGDMA soc-mode ED.
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