Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide

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ID 823179
Date 4/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Description 2. Quick Start Guide 3. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide
1. Design Example Description x
1.1. H2D ST to D2H ST Loopback Design Example
1.1. H2D ST to D2H ST Loopback Design Example x
1.1.1. DMA PCIe* Mode Design Example 1.1.2. DMA SoC Mode Design Example
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Testbench 2.5. Compiling the Design Example 2.6. Hardware and Software Requirements 2.7. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. DMA SoC Mode Example Design 2.3.2. DMA PCIe Mode Example Design
2.3.2. DMA PCIe Mode Example Design x
2.3.2.1. Running Simulation using VCS* MX 2.3.2.2. Running Simulation Using QuestaSim* 2.3.2.3. Running Simulation using Xcelium 2.3.2.4. Running Simulation using Riviera-PRO
2.4. Testbench x
2.4.1. DMA SoC Mode H2D ST to D2H ST Loopback Example Testbench 2.4.2. DMA PCIe Mode H2D ST to D2H ST Loopback & H2D MM Example Testbench
2.4.2. DMA PCIe Mode H2D ST to D2H ST Loopback & H2D MM Example Testbench x
2.4.2.1. Design Example Testbench
2.7. Running the Design Example x
2.7.1. Running the DMA SoC Mode H2D ST to D2H ST Loopback Design Example 2.7.2. Running the DMA PCIe Mode H2D ST to D2H ST Loopback Design Example
2.7.1. Running the DMA SoC Mode H2D ST to D2H ST Loopback Design Example x
2.7.1.1. Building the Software Application Project for Nios® V/m Processor 2.7.1.2. Programming the Example Design into the Development Board
2.7.2. Running the DMA PCIe Mode H2D ST to D2H ST Loopback Design Example x
2.7.2.1. Installing the Linux Kernel Driver 2.7.2.2. Running the Loopback Design Example
2.7.2.2. Running the Loopback Design Example x
2.7.2.2.1. Testing H2D ST to D2H ST Loopback 2.7.2.2.2. Testing H2D MM
1. Design Example Description
2. Quick Start Guide
3. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide

2.4.1. DMA SoC Mode H2D ST to D2H ST Loopback Example Testbench

This design example demonstrates an H2D ST to D2H ST loopback simulation for DMA SoC mode.

The design example simulation demonstrates the following sequences, which are set up via the Nios® V Subsystem from application software and driver:

  1. Identifies the number of device ports and corresponding types via IP_PARAM register from the Global CSR during the initialization.
  2. Performs soft reset sequence on Prefetcher Engine and device ports via the corresponding registers from Global CSR and Device Port CSR during the initialization.
  3. Enables Prefetcher Engine via CTRL register from the Global CSR.
  4. Initialize the corresponding H2D ST and D2H ST device ports via the corresponding registers from Device Port CSR.
  5. Setup corresponding data and responder descriptor buffers for both H2D ST and D2H ST device ports.
  6. Updates the corresponding Q_INSERT_POINTER registers from Device Port CSR for both H2D ST and D2H ST device ports.
  7. The application software verifies the data transfer completion via Nios® V Subsystem in the following ways:
    • For the H2D ST device port, the Q_EXTRACT_POINTER register is polled to identify if the value updated by hardware matches the Q_INSERT_POINTER value configured by the software.
    • For the D2H ST device port, the user-defined interrupt service routine is called upon receiving an interrupt issued from hardware to the Nios® V Subsystem.
  8. Analyzes the content of the responder descriptors written from hardware.
  9. Compares the data written back from the D2H ST device port against the data sent over to hardware that outputs at the H2D ST device port.
  10. Performs soft reset sequence on Prefetcher Engine and device ports via the corresponding registers from Global CSR and Device Port CSR after data transfer completion.
Figure 10. Simulation Waveform for the H2D ST to D2H ST Loopback Design Example
Figure 11. Simulation Output Results
Figure 12. Simulation Output Results (cont.)
Figure 13. Simulation Output Results (cont.)
The following sample output illustrates a successful simulation test run for the Questasim simulator.
Note: If you want to add signals to the waveform for monitoring or debugging, first run the run_msim_setup.tcl script in Questasim. Then, run the ld_debug command and add the signals you want to monitor in the waveform window. Finally, run the command run –all. 
Sample output from simulation
********************************************************************************
# INFO: Altera sSGDMA multiport AXI-ST loopback & AXI4-MM memory access soc-mode example
# INFO: ********************************************************************************
# INFO: Enabling prefetcher!
# INFO: Enable prefetcher: ret 0, enable 1
# INFO: Dev csr base: 0x400000. total port 3
# INFO: *******************************************************************************
# INFO: Streaming Interface -- start loopback transfer for  H2D-ST0-->>>>>>--D2H-ST0 
# INFO: *******************************************************************************
# INFO: Fill H2D ST ret 0, length 192 bytes
# INFO: Fill H2D ST ret 0, length 192 bytes
# INFO: Fill H2D ST ret 0, length 192 bytes
# INFO: Creating decriptors below for non-contiguous memory trasfer => Scatter-Gather operation..!!!
# INFO: Fill H2D ST ret 0, length 320 bytes, src_adr mem loc {[start => 0x295a0 ~~~ end => 0x296df]}
# INFO: Fill H2D ST ret 0, length 640 bytes, src_adr mem loc {[start => 0x298c0 ~~~ end => 0x29b3f]}
# INFO: Fill H2D ST ret 0, length 480 bytes, src_adr mem loc {[start => 0x296e0 ~~~ end => 0x298bf]}
# INFO: H2D_ST update insert ptr ret 0.
# INFO: H2D_ST insert ptr ret 0, val 7
# INFO: Interrupt D2H_ST before: 0.
# INFO: Creating multiple decriptors (maximum payload/data length 96 bytes for each decriptor)..
# INFO: Fill D2H ST ret 0, length 576 bytes
# INFO: Number of D2H-ST descriptors created for length 576 bytes based on configured MAX_DESC_LENGTH == 6 
# INFO: Fill D2H ST ret 0, length 320 bytes, dest_adr mem loc {[start => 0x29d80 ~~~ end => 0x29ebf]}
# INFO: Fill D2H ST ret 0, length 640 bytes, dest_adr mem loc {[start => 0x2a0a0 ~~~ end => 0x2a31f]}
# INFO: Fill D2H ST ret 0, length 480 bytes, dest_adr mem loc {[start => 0x29ec0 ~~~ end => 0x2a09f]}
# INFO: D2H_ST update insert ptr ret 0.
# INFO: D2H_ST insert ptr ret 0, val 10
# INFO: check H2D_ST for complete.
# INFO: H2D_ST resp before poll for completion called..
# INFO: resp format 0x13, Idx 2, length 192 bytes, status 0x80
# INFO: resp format 0x13, Idx 3, length 192 bytes, status 0x80
# INFO: resp format 0x13, Idx 4, length 192 bytes, status 0x81
# INFO: resp format 0x13, Idx 5, length 320 bytes, status 0x80
# INFO: resp format 0x13, Idx 6, length 640 bytes, status 0x80
# INFO: resp format 0x13, Idx 7, length 480 bytes, status 0x81
# INFO: HW Extract pointer after H2D_ST 7, ret 0
# INFO: H2D_ST complete ret 0, last idx 7
# INFO: H2D_ST resp after poll for completion called..
# INFO: resp format 0x13, Idx 2, length 192 bytes, status 0x0
# INFO: resp format 0x13, Idx 3, length 192 bytes, status 0x0
# INFO: resp format 0x13, Idx 4, length 192 bytes, status 0x1
# INFO: resp format 0x13, Idx 5, length 320 bytes, status 0x0
# INFO: resp format 0x13, Idx 6, length 640 bytes, status 0x0
# INFO: resp format 0x13, Idx 7, length 480 bytes, status 0x1
# INFO: D2H_ST status before interrupt.
# INFO: gcsr status: val 0x80000000
# INFO: gcsr irq status: val 0x1
# INFO: type 0, status: ret 0, val 0x90000014
# INFO: interrupt cnt 0, completed desc 0
# INFO: D2H_ST resp before interrupt enabled.
# INFO: resp format 0x17, Idx 2, length 96 bytes, status 0x80
# INFO: resp format 0x17, Idx 3, length 96 bytes, status 0x80
# INFO: resp format 0x17, Idx 4, length 96 bytes, status 0x80
# INFO: resp format 0x17, Idx 5, length 96 bytes, status 0x80
# INFO: resp format 0x17, Idx 6, length 96 bytes, status 0x80
# INFO: resp format 0x17, Idx 7, length 96 bytes, status 0x81
# INFO: resp format 0x17, Idx 8, length 320 bytes, status 0x80
# INFO: resp format 0x17, Idx 9, length 640 bytes, status 0x80
# INFO: resp format 0x17, Idx 10, length 480 bytes, status 0x85
# INFO: D2H_ST status after interrupt enabled.
# INFO: gcsr status: val 0x0
# INFO: gcsr irq status: val 0x0
# INFO: type 0, status: ret 0, val 0x14
# INFO: interrupt cnt 1, completed desc 9
# INFO: HW Extract pointer after D2H_ST 10, ret 0
# INFO: D2H_ST resp after interrupt.
# INFO: resp format 0x17, Idx 2, length 96 bytes, status 0x0
# INFO: resp format 0x17, Idx 3, length 96 bytes, status 0x0
# INFO: resp format 0x17, Idx 4, length 96 bytes, status 0x0
# INFO: resp format 0x17, Idx 5, length 96 bytes, status 0x0
# INFO: resp format 0x17, Idx 6, length 96 bytes, status 0x0
# INFO: resp format 0x17, Idx 7, length 96 bytes, status 0x1
# INFO: resp format 0x17, Idx 8, length 320 bytes, status 0x0
# INFO: resp format 0x17, Idx 9, length 640 bytes, status 0x0
# INFO: resp format 0x17, Idx 10, length 480 bytes, status 0x5
# INFO: Transfered data matches with received data..!!!
# INFO: Total streamed transfer length = 2016 bytes
# INFO: ********************************************************************
# INFO: ********************************************************************
# INFO: Memory Mapped Interface -- start transfer for H2D-MM0-->>>>>>--OCM 
# INFO: ********************************************************************
# INFO: Fill H2D MM ret 0, length 1024 bytes
# INFO: update insert ptr ret 0.
# INFO: After update Insert pointer H2D_MM 2, ret 0
# INFO: D2H_MM update insert ptr ret 0.
# INFO: Creating multiple decriptors (maximum payload/data length 96 bytes for each decriptor)..
# INFO: Fill D2H MM ret 0, length 1024 bytes
# INFO: Number of D2H-MM descriptors created for length 1024 bytes based on configured MAX_DESC_LENGTH == 11 
# INFO: D2H_MM update insert ptr ret 0.
# INFO: D2H_MM insert ptr ret 0, val 13
# INFO: check H2D_MM for complete.
# INFO: irq count 2, irq complete 11, poll complete 0
# INFO: H2D_MM complete ret 0, last idx 13
# INFO: HW Extract pointer after H2D_MM 13, ret 0
# INFO: H2D MM resp.
# INFO: resp format 0xb, Idx 2, length 1024 bytes, status 0x8
# INFO: resp format 0xb, Idx 3, length 96 bytes, status 0x0
# INFO: resp format 0xb, Idx 4, length 96 bytes, status 0x0
# INFO: resp format 0xb, Idx 5, length 96 bytes, status 0x0
# INFO: resp format 0xb, Idx 6, length 96 bytes, status 0x0
# INFO: resp format 0xb, Idx 7, length 96 bytes, status 0x0
# INFO: resp format 0xb, Idx 8, length 96 bytes, status 0x0
# INFO: resp format 0xb, Idx 9, length 96 bytes, status 0x0
# INFO: resp format 0xb, Idx 10, length 96 bytes, status 0x0
# INFO: resp format 0xb, Idx 11, length 96 bytes, status 0x0
# INFO: resp format 0xb, Idx 12, length 96 bytes, status 0x0
# INFO: resp format 0xb, Idx 13, length 64 bytes, status 0x8
# INFO: gcsr status: val 0x0
# INFO: gcsr irq status: val 0x0
# INFO: type 2, status: ret 0, val 0x14
# INFO: interrupt cnt 2, completed desc 11
# INFO: Transfered to onchip memory connected to sSGDMA AXI4-MM interface completed
# INFO: Data matches with received data!! Total memory transfer length = 1024 bytes
# INFO: Free resources!
# INFO: Reset Ports!
# INFO: Memory copy over DMA sucessfully compleated..!!! End of sSGDMA soc-mode ED.
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