Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide

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ID 823179
Date 4/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Description 2. Quick Start Guide 3. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide
1. Design Example Description x
1.1. H2D ST to D2H ST Loopback Design Example
1.1. H2D ST to D2H ST Loopback Design Example x
1.1.1. DMA PCIe* Mode Design Example 1.1.2. DMA SoC Mode Design Example
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Testbench 2.5. Compiling the Design Example 2.6. Hardware and Software Requirements 2.7. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. DMA SoC Mode Example Design 2.3.2. DMA PCIe Mode Example Design
2.3.2. DMA PCIe Mode Example Design x
2.3.2.1. Running Simulation using VCS* MX 2.3.2.2. Running Simulation Using QuestaSim* 2.3.2.3. Running Simulation using Xcelium 2.3.2.4. Running Simulation using Riviera-PRO
2.4. Testbench x
2.4.1. DMA SoC Mode H2D ST to D2H ST Loopback Example Testbench 2.4.2. DMA PCIe Mode H2D ST to D2H ST Loopback & H2D MM Example Testbench
2.4.2. DMA PCIe Mode H2D ST to D2H ST Loopback & H2D MM Example Testbench x
2.4.2.1. Design Example Testbench
2.7. Running the Design Example x
2.7.1. Running the DMA SoC Mode H2D ST to D2H ST Loopback Design Example 2.7.2. Running the DMA PCIe Mode H2D ST to D2H ST Loopback Design Example
2.7.1. Running the DMA SoC Mode H2D ST to D2H ST Loopback Design Example x
2.7.1.1. Building the Software Application Project for Nios® V/m Processor 2.7.1.2. Programming the Example Design into the Development Board
2.7.2. Running the DMA PCIe Mode H2D ST to D2H ST Loopback Design Example x
2.7.2.1. Installing the Linux Kernel Driver 2.7.2.2. Running the Loopback Design Example
2.7.2.2. Running the Loopback Design Example x
2.7.2.2.1. Testing H2D ST to D2H ST Loopback 2.7.2.2.2. Testing H2D MM
1. Design Example Description
2. Quick Start Guide
3. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP Design Example User Guide

2.2. Generating the Design Example

Figure 7. Procedure
  1. In the Quartus® Prime Pro Edition software, create a new project (File > New Project Wizard).
  2. Specify the Directory, Name and Top-Level Entity.
  3. For Family, Device & Board Settings, select Agilex™ 5 (E-series/D-series) and for Target Device, select A5ED065BB32AE6SR0 for your design.
  4. Click Finish.
  5. In the IP catalog, locate and add the Scalable Scatter-Gather DMA Intel® FPGA IP .
  6. In the New IP Variant dialog box, specify a name for your IP. Click Create.
  7. In the IP Parameter Editor, specify the parameters for your IP variation.
    Note: For DMA PCIe and SOC Mode: Number of H2D ST and D2H ST device ports must be the same and only one H2D MM device port setting is supported.
    Note: For DMA PCIe Mode only: Optional BAM interface is not supported. Only 128-bit TLP streaming interface width example design is supported on hardware.
  8. On the Example Design tab, make the following selections:
    1. For Generate Example Design, only the Synthesis and Synthesis & Simulation options are available for DMA PCIe* Mode Design Example. Synthesis, Simulation, and Synthesis & Simulation options are available for DMA SoC Mode Design Example.
    2. Example Design Mode option is automatically populated.
    3. For Target Development Kit, select either the Agilex 5 FPGA E-Series 065B Modular Development Kit or NONE to target the device selected for your current Quartus® Prime software project. If you select the development kit, the settings including the pin assignments are included in the .qsf file of the generated design example, and you are not required to add them manually. These settings are board-specific for the development kit.
  9. Select Generate Example Design to create a design example you can compile and simulate. When the prompt asks you to specify the directory for your design example, you can accept the default ./intel_ssgdma_0_ed/ directory or choose another directory.
  10. Click Finish. You may save your .ip file when prompted, but it is not required to be able to use the design example.
Figure 8. Example Design Tab
Level Two Title