GTS Interlaken Intel® FPGA IP User Guide

ID 819200
Date 3/31/2024
Document Table of Contents

1. About the GTS Interlaken FPGA IP Core

Updated for:
Intel® Quartus® Prime Design Suite 24.1
IP Version 3.0.0

Interlaken is a high-speed serial communication protocol for chip-to-chip packet transfers at rates from 10 Gbps to 200 Gbps and beyond. It builds on the channelization and per channel flow control features of SPI-4.2, while reducing the number of I/O pins by using high speed SerDes technology.

Interlaken provides low I/O count compared to earlier protocols, supporting scalability in both number of lanes and lane speed. Other key features include flow control, low overhead framing, and extensive integrity checking. The Interlaken IP incorporates a physical coding sublayer (PCS), a physical media attachment (PMA), and a media access control (MAC) block.

Figure 1. Typical Interlaken Application