GTS Interlaken Intel® FPGA IP User Guide

ID 819200
Date 3/31/2024
Public

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1.4. Performance and Resource Utilization

This section covers the resources and expected performance numbers for selected variations of the Interlaken IP core using the Quartus® Prime Pro Edition software. Your results may slightly vary depending on the device you select.

For a comprehensive list of supported configurations, refer to Table 1. IP Supported Combinations of Number of Lanes and Data Rates

Table 4.  Resource Utilization for Multi-Segment (Number of Segments = 1)
Transceiver Mode PMA Type Data Rate (Gbps) Number of Lanes ALM Logic Register (Primary) Logic Register (Secondary) M20k
NRZ FGT 6.25 4 22304.4 38,925 7,974 32
12.5 4 22342.7 38,829 8,044 32
8 46372.8 77,856 14,864 60
Table 5.  Resource Utilization for Multi-Segment (Packet)
Transceiver Mode PMA Type Data Rate (Gbps) Number of Lanes ALM Logic Register (Primary) Logic Register (Secondary) M20k
NRZ FGT 6.25 4 22418.6 38,945 8,021 32
12.5 4 22374.3 38,865 8,096 32
8 46362.9 78,199 14,430 60