Test Engine FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

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ID 817758
Date 5/31/2024
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Document Table of Contents
Document Table of Contents x
1. About the Test Engine FPGA IP 2. Test Engine IP - Introduction 3. Parameterizing the Test Engine IP 4. Test Engine IP - Interface Signals 5. Test Engine IP - Software 6. Test Engine IP - Limitations 7. Document Revision History for the Test Engine FPGA IP User Guide
1. About the Test Engine FPGA IP x
1.1. Release Information
2. Test Engine IP - Introduction x
2.1. Test Engine IP Feature Support
3. Parameterizing the Test Engine IP x
3.1. Parameters 3.2. Drivers Parameters 3.3. Remote Access Parameters
3.2. Drivers Parameters x
3.2.1. CSR AXI4-Lite Driver Parameters 3.2.2. Memory AXI4 Driver Parameters 3.2.3. Memory Status Driver Parameters 3.2.4. Memory Reset Driver Parameters 3.2.5. CAM AXI4-Stream Driver Parameters
4. Test Engine IP - Interface Signals x
4.1. Remote Interface Signals 4.2. I/O PLL Interface Signals 4.3. Status Interface Signals 4.4. Global CSR interface Signals 4.5. Memory AXI4 Driver Interface Signals 4.6. CSR AXI-Lite Driver Interface Signals 4.7. Memory Status Driver Interface Signals 4.8. Memory Reset Driver Interface Signals 4.9. CAM AXI-Stream Driver Interface Signals 4.10. Registers
4.10. Registers x
4.10.1. Global Control Registers 4.10.2. Memory AXI4 Driver Registers 4.10.3. CSR AXI4-Lite Driver Registers 4.10.4. Memory Status Driver Registers 4.10.5. Memory Reset Driver Registers 4.10.6. CAM AXI4-Stream Driver Registers
4.10.1. Global Control Registers x
4.10.1.1. version_0 4.10.1.2. version_1 4.10.1.3. ctrl_status_0 4.10.1.4. driver_ctrl_status_1 4.10.1.5. driver_run_bitmask_0 4.10.1.6. driver_run_bitmask_1 4.10.1.7. driver_run_bitmask_2 4.10.1.8. driver_run_bitmask3 4.10.1.9. driver_done_bitmask_0 4.10.1.10. driver_done_bitmask_1 4.10.1.11. driver_done_bitmask_2 4.10.1.12. driver_done_bitmask_3 4.10.1.13. driver_error_bitmask_0 4.10.1.14. driver_error_bitmask_1 4.10.1.15. driver_error_bitmask_2 4.10.1.16. driver_error_bitmask_3
4.10.2. Memory AXI4 Driver Registers x
4.10.2.1. version_lo 4.10.2.2. version_hi 4.10.2.3. ctrl_stat_lo 4.10.2.4. ctrl_stat_hi 4.10.2.5. scratchpad_lo 4.10.2.6. scratchpad_hi 4.10.2.7. wr_log_ram_stat_lo 4.10.2.8. wr_log_ram_stat_hi 4.10.2.9. wr_log_ram_ctrl_lo 4.10.2.10. wr_log_ram_ctrl_hi 4.10.2.11. rd_log_ram_stat_lo 4.10.2.12. rd_log_ram_stat_hi 4.10.2.13. rd_log_ram_ctrl_lo 4.10.2.14. rd_log_ram_ctrl_hi 4.10.2.15. wr_err_counters_0_lo 4.10.2.16. wr_err_counters_0_hi 4.10.2.17. rd_err_counters_0_lo 4.10.2.18. rd_err_counters_0_hi 4.10.2.19. rd_err_counters_1_lo 4.10.2.20. rd_err_counters_1_hi 4.10.2.21. rd_pnf_0_lo 4.10.2.22. rd_pnf_0_hi 4.10.2.23. rd_pnf_1_lo 4.10.2.24. rd_pnf_1_hi 4.10.2.25. rd_pnf_2_lo 4.10.2.26. rd_pnf_2_hi 4.10.2.27. rd_pnf_3_lo 4.10.2.28. rd_pnf_3_hi 4.10.2.29. rd_pnf_4_lo 4.10.2.30. rd_pnf_4_hi 4.10.2.31. rd_pnf_5_lo 4.10.2.32. rd_pnf_5_hi 4.10.2.33. rd_pnf_6_lo 4.10.2.34. rd_pnf_6_hi 4.10.2.35. rd_pnf_7_lo 4.10.2.36. rd_pnf_7_hi 4.10.2.37. rd_pnf_8_lo 4.10.2.38. rd_pnf_8_hi 4.10.2.39. rd_pnf_9_lo 4.10.2.40. rd_pnf_9_hi 4.10.2.41. rd_pnf_10_lo 4.10.2.42. rd_pnf_10_hi 4.10.2.43. rd_pnf_11_lo 4.10.2.44. rd_pnf_11_hi 4.10.2.45. rd_pnf_12_lo 4.10.2.46. rd_pnf_12_hi 4.10.2.47. rd_pnf_13_lo 4.10.2.48. rd_pnf_13_hi 4.10.2.49. rd_pnf_14_lo 4.10.2.50. rd_pnf_14_hi 4.10.2.51. rd_pnf_15_lo 4.10.2.52. rd_pnf_15_hi 4.10.2.53. rd_pnf_16_lo 4.10.2.54. rd_pnf_16_hi 4.10.2.55. rd_pnf_17_lo 4.10.2.56. rd_pnf_17_hi 4.10.2.57. rd_pnf_18_lo 4.10.2.58. rd_pnf_18_hi 4.10.2.59. rd_pnf_19_lo 4.10.2.60. rd_pnf_19_hi 4.10.2.61. ter_dq_mask_0_lo 4.10.2.62. ter_dq_mask_0_hi 4.10.2.63. ter_dq_mask_1_lo 4.10.2.64. ter_dq_mask_1_hi 4.10.2.65. ter_lo 4.10.2.66. ter_hi
1. About the Test Engine FPGA IP
2. Test Engine IP - Introduction
3. Parameterizing the Test Engine IP
4. Test Engine IP - Interface Signals
5. Test Engine IP - Software
6. Test Engine IP - Limitations
7. Document Revision History for the Test Engine FPGA IP User Guide

4.8. Memory Reset Driver Interface Signals

Table 26.  Clock and Reset Signals
Port Name Width Direction Description
driver#_clk 1 Input Clock Input for the Memory Reset Driver. This is the clock that will be used for the reset interface.
driver#_reset_n 1 Input Reset Input for the Memory Reset Driver. Asserting this reset will reset the traffic generation logic and the CSR registers.
driver#_csr_clk 1 Input Clock Input for the Memory Reset Driver sideband interface.
driver#_csr_reset_n 1 Input Reset Input for the Memory Reset Driver sideband interface.
Note: For the driver#_* ports, # is the driver index.
Table 27.  Memory Subsystem Reset Conduit Signals
Port Name Width Direction Description
driver#_app_ss_rst_req 1 Output Signal from user logic to request the memory interface to be reset and recalibrated. Active high synchronous signal. Synchronized to the app_ss_mem_usr_clk clock.
driver#_ss_app_rst_rdy 1 Input Signal from memory interface to indicate whether it has completed a reset sequence, is currently out of reset, and is ready for a new reset request. Active high synchronous signal. Synchronized to the app_ss_mem_usr_clk clock
driver#_app_ss_cold_rst_n 1 Output Resets the functionality of the memory subsystem. Resets all sticky bits. This signal is active-LOW. Applicable when memory subsystem has sticky bits.
driver#_ss_app_cold_rst_ack_n 1 Input Reset handshake. On of the use case is to serve as feedback that the reset is already effectuated when the corresponding reset is implemented as synchronous reset
Note: For the driver#_* ports, # is the driver index.
Table 28.  Sideband AXI4-Lite Signals
Port Name Width Direction Description
driver#_csr_axi4l_awaddr 22 Input Write address.
driver#_csr_axi4l_awvalid 1 Input Write Address Channel Valid. This signal indicates that valid write address and control information are available.
driver#_csr_axi4l_awready 1 Output Write Address Channel Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
driver#_csr_axi4l_awprot 3 Input Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
driver#_csr_axi4l_araddr 22 Input Read address.
driver#_csr_axi4l_arvalid 1 Input Read Address Valid. This signal indicates that valid read address and control information are available.
driver#_csr_axi4l_arready 1 Output Read Address Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
driver#_csr_axi4l_arprot 3 Input Protection Type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
driver#_csr_axi4l_wdata 32 Input Write data.
driver#_csr_axi4l_wstrb 4 Input Write Strobes (Byte Enables).
driver#_csr_axi4l_wvalid 1 Input Write Response Channel Valid. This signal indicates that a valid write response is available.
driver#_csr_axi4l_wready 1 Output Write Response Channel Ready. This signal indicates that the manager can accept a write response.
driver#_csr_axi4l_bresp 2 Output Write Response. This signal indicates the result of the Write command.
driver#_csr_axi4l_bvalid 1 Output Write Response Channel Valid. This signal indicates that a valid write response is available.
driver#_csr_axi4l_bready 1 Input Write Response Channel Ready. This signal indicates that the manager can accept a write response.
driver#_csr_axi4l_rdata 32 Output Read data.
driver#_csr_axi4l_rresp 2 Output Read response. This signal indicates the status of the read transfer.
driver#_csr_axi4l_rvalid 1 Output Read Valid. This signal indicates that a valid read response is available.
driver#_csr_axi4l_rready 1 Input Read Response Channel Ready. This signal indicates that the manager can accept the read data and response information.
Note: For the driver#_* ports, # is the driver index.

The Sideband CSR ports are available only when the Remote Access > Configuration Interface parameter is set to Export.

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