Test Engine FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

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Date 5/31/2024
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Document Table of Contents
Document Table of Contents x
1. About the Test Engine FPGA IP 2. Test Engine IP - Introduction 3. Parameterizing the Test Engine IP 4. Test Engine IP - Interface Signals 5. Test Engine IP - Software 6. Test Engine IP - Limitations 7. Document Revision History for the Test Engine FPGA IP User Guide
1. About the Test Engine FPGA IP x
1.1. Release Information
2. Test Engine IP - Introduction x
2.1. Test Engine IP Feature Support
3. Parameterizing the Test Engine IP x
3.1. Parameters 3.2. Drivers Parameters 3.3. Remote Access Parameters
3.2. Drivers Parameters x
3.2.1. CSR AXI4-Lite Driver Parameters 3.2.2. Memory AXI4 Driver Parameters 3.2.3. Memory Status Driver Parameters 3.2.4. Memory Reset Driver Parameters 3.2.5. CAM AXI4-Stream Driver Parameters
4. Test Engine IP - Interface Signals x
4.1. Remote Interface Signals 4.2. I/O PLL Interface Signals 4.3. Status Interface Signals 4.4. Global CSR interface Signals 4.5. Memory AXI4 Driver Interface Signals 4.6. CSR AXI-Lite Driver Interface Signals 4.7. Memory Status Driver Interface Signals 4.8. Memory Reset Driver Interface Signals 4.9. CAM AXI-Stream Driver Interface Signals 4.10. Registers
4.10. Registers x
4.10.1. Global Control Registers 4.10.2. Memory AXI4 Driver Registers 4.10.3. CSR AXI4-Lite Driver Registers 4.10.4. Memory Status Driver Registers 4.10.5. Memory Reset Driver Registers 4.10.6. CAM AXI4-Stream Driver Registers
4.10.1. Global Control Registers x
4.10.1.1. version_0 4.10.1.2. version_1 4.10.1.3. ctrl_status_0 4.10.1.4. driver_ctrl_status_1 4.10.1.5. driver_run_bitmask_0 4.10.1.6. driver_run_bitmask_1 4.10.1.7. driver_run_bitmask_2 4.10.1.8. driver_run_bitmask3 4.10.1.9. driver_done_bitmask_0 4.10.1.10. driver_done_bitmask_1 4.10.1.11. driver_done_bitmask_2 4.10.1.12. driver_done_bitmask_3 4.10.1.13. driver_error_bitmask_0 4.10.1.14. driver_error_bitmask_1 4.10.1.15. driver_error_bitmask_2 4.10.1.16. driver_error_bitmask_3
4.10.2. Memory AXI4 Driver Registers x
4.10.2.1. version_lo 4.10.2.2. version_hi 4.10.2.3. ctrl_stat_lo 4.10.2.4. ctrl_stat_hi 4.10.2.5. scratchpad_lo 4.10.2.6. scratchpad_hi 4.10.2.7. wr_log_ram_stat_lo 4.10.2.8. wr_log_ram_stat_hi 4.10.2.9. wr_log_ram_ctrl_lo 4.10.2.10. wr_log_ram_ctrl_hi 4.10.2.11. rd_log_ram_stat_lo 4.10.2.12. rd_log_ram_stat_hi 4.10.2.13. rd_log_ram_ctrl_lo 4.10.2.14. rd_log_ram_ctrl_hi 4.10.2.15. wr_err_counters_0_lo 4.10.2.16. wr_err_counters_0_hi 4.10.2.17. rd_err_counters_0_lo 4.10.2.18. rd_err_counters_0_hi 4.10.2.19. rd_err_counters_1_lo 4.10.2.20. rd_err_counters_1_hi 4.10.2.21. rd_pnf_0_lo 4.10.2.22. rd_pnf_0_hi 4.10.2.23. rd_pnf_1_lo 4.10.2.24. rd_pnf_1_hi 4.10.2.25. rd_pnf_2_lo 4.10.2.26. rd_pnf_2_hi 4.10.2.27. rd_pnf_3_lo 4.10.2.28. rd_pnf_3_hi 4.10.2.29. rd_pnf_4_lo 4.10.2.30. rd_pnf_4_hi 4.10.2.31. rd_pnf_5_lo 4.10.2.32. rd_pnf_5_hi 4.10.2.33. rd_pnf_6_lo 4.10.2.34. rd_pnf_6_hi 4.10.2.35. rd_pnf_7_lo 4.10.2.36. rd_pnf_7_hi 4.10.2.37. rd_pnf_8_lo 4.10.2.38. rd_pnf_8_hi 4.10.2.39. rd_pnf_9_lo 4.10.2.40. rd_pnf_9_hi 4.10.2.41. rd_pnf_10_lo 4.10.2.42. rd_pnf_10_hi 4.10.2.43. rd_pnf_11_lo 4.10.2.44. rd_pnf_11_hi 4.10.2.45. rd_pnf_12_lo 4.10.2.46. rd_pnf_12_hi 4.10.2.47. rd_pnf_13_lo 4.10.2.48. rd_pnf_13_hi 4.10.2.49. rd_pnf_14_lo 4.10.2.50. rd_pnf_14_hi 4.10.2.51. rd_pnf_15_lo 4.10.2.52. rd_pnf_15_hi 4.10.2.53. rd_pnf_16_lo 4.10.2.54. rd_pnf_16_hi 4.10.2.55. rd_pnf_17_lo 4.10.2.56. rd_pnf_17_hi 4.10.2.57. rd_pnf_18_lo 4.10.2.58. rd_pnf_18_hi 4.10.2.59. rd_pnf_19_lo 4.10.2.60. rd_pnf_19_hi 4.10.2.61. ter_dq_mask_0_lo 4.10.2.62. ter_dq_mask_0_hi 4.10.2.63. ter_dq_mask_1_lo 4.10.2.64. ter_dq_mask_1_hi 4.10.2.65. ter_lo 4.10.2.66. ter_hi
1. About the Test Engine FPGA IP
2. Test Engine IP - Introduction
3. Parameterizing the Test Engine IP
4. Test Engine IP - Interface Signals
5. Test Engine IP - Software
6. Test Engine IP - Limitations
7. Document Revision History for the Test Engine FPGA IP User Guide

3.2.2. Memory AXI4 Driver Parameters

Figure 5. Group: Drivers / Address Generation

Table 6.  Group: Drivers / Address Generation
Display Name Description
Address ALU argument width Specifies the width of the Address ALU. This affects the number of bits the Address ALU can change. Increasing this will allow wider ranges of address sweeping per command, but could degrade Fmax. The supported range for this parameter is from 1 to 44. Default value is 16.
Fast clip recovery If enabled, address will reset to lower bound for 1 cycle when it exceeds upper bound, else it will reset to lower bound for 2 cycles – where lower bound is the minimum value of the defined address range, and upper bound is the maximum value of the defined address range. Enabling this can reduce latency for looped addresses, but can also degrade Fmax.
Number of address fields Address fields allow updating selective bits (for example, field) within the address. The supported range for this parameter is from 1 to 8. Default value is 1.
Address field 0 bitmask Update selective bits (for example, field) within the address by specifying a bitmask for the field. The main usage of address fields is to selectively choose which bits to affect.

The supported range for this parameter is 0x0000_0000_0000_0000 to 0xffff_ffff_ffff_ffff. Default value is 0xffff_ffff_ffff_ffff.
Address field 1 bitmask Update selective bits (i.e. field) within the address by specifying a bitmask for the field. The main usage of address fields is to selectively choose which bits to affect.

The supported range for this parameter is 0x0000_0000_0000_0000 to 0xffff_ffff_ffff_ffff. Default value is 0xffff_ffff_ffff_ffff.
Address field 2 bitmask Update selective bits (i.e. field) within the address by specifying a bitmask for the field. The main usage of address fields is to selectively choose which bits to affect.

The supported range for this parameter is 0x0000_0000_0000_0000 to 0xffff_ffff_ffff_ffff. Default value is 0xffff_ffff_ffff_ffff.
Address field 3 bitmask Update selective bits (i.e. field) within the address by specifying a bitmask for the field. The main usage of address fields is to selectively choose which bits to affect.

The supported range for this parameter is 0x0000_0000_0000_0000 to 0xffff_ffff_ffff_ffff. Default value is 0xffff_ffff_ffff_ffff.
Address field 4 bitmask Update selective bits (i.e. field) within the address by specifying a bitmask for the field. The main usage of address fields is to selectively choose which bits to affect.

The supported range for this parameter is 0x0000_0000_0000_0000 to 0xffff_ffff_ffff_ffff. Default value is 0xffff_ffff_ffff_ffff.
Address field 5 bitmask Update selective bits (i.e. field) within the address by specifying a bitmask for the field. The main usage of address fields is to selectively choose which bits to affect.

The supported range for this parameter is 0x0000_0000_0000_0000 to 0xffff_ffff_ffff_ffff. Default value is 0xffff_ffff_ffff_ffff.
Address field 6 bitmask Update selective bits (i.e. field) within the address by specifying a bitmask for the field. The main usage of address fields is to selectively choose which bits to affect.

The supported range for this parameter is 0x0000_0000_0000_0000 to 0xffff_ffff_ffff_ffff. Default value is 0xffff_ffff_ffff_ffff.
Address field 7 bitmask Update selective bits (i.e. field) within the address by specifying a bitmask for the field. The main usage of address fields is to selectively choose which bits to affect.

The supported range for this parameter is 0x0000_0000_0000_0000 to 0xffff_ffff_ffff_ffff. Default value is 0xffff_ffff_ffff_ffff.
Figure 6. Group: Drivers / Data Generation

Table 7.  Group: Drivers / Data Generation
Display Name Description
Number of DQ generators Memory DQ pins can be driven by distinct pattern generators. If there are more DQ pins than generators, the patterns will be replicated. If there are fewer DQ pins than generators, the unused generators are discarded.

The supported values for this parameter are: 1, 2, 4, 8, 16. Default value is 2.
Number of DM generators Memory DM pins can be driven by distinct pattern generators. If there are more DM pins than generators, the patterns will be replicated. If there are fewer DM pins than generators, the unused generators are discarded.

The supported values for this parameter are: 1, 2, 4, 8. Default value is 2.
AXI-data / Memory-DQ width ratio Ratio between AXI data width and Memory DQ width, which affects the unroll factor of DQ and DM generators. (Memory-DQ Width Ratio = Data Width ÷ DQ Width).
Figure 7. Group: Drivers / AXI4 Ports

Table 8.  Group: Drivers / AXI4 Ports
Display Name Description
Write ID Width Specifies widths of AWID and BID ports of the AXI4 bus. The supported range for this parameter is from 1 to 18. Default value is 7.
Write Address Width Specifies width of AWADDR port of the AXI4 bus. The supported range for this parameter is from 1 to 64. Default value is 31.
Use AWLOCK Use AWLOCK port on the AXI4 bus.
Use AWCACHE Use AWCACHE port on the AXI4 bus.
Use AWQOS Use AWQOS port on the AXI4 bus.
Use AWREGION Use AWREGION port on the AXI4 bus.
Use AWUSER Use AWUSER port on the AXI4 bus.
AWUSER Width Specifies width of AWUSER port of the AXI4 bus. The supported range for this parameter is from 1 to 64. Default value is 8.
Read ID Width Specifies widths of ARID and RID ports of the AXI4 bus. The supported range for this parameter is from 1 to 18. Default value is 7.
Read Address Width Specifies width of ARADDR port of the AXI4 bus. The supported range for this parameter is from 1 to 64. Default value is 31.
Use ARLOCK Use ARLOCK port on the AXI4 bus.
Use ARCACHE Use ARCACHE port on the AXI4 bus.
Use ARQOS Use ARQOS port on the AXI4 bus.
Use ARREGION Use ARREGION port on the AXI4 bus.
Use ARUSER Use ARUSER port on the AXI4 bus.
ARUSER Width Specifies width of ARUSER port of the AXI4 bus. The supported range for this parameter is from 1 to 64. Default value is 8.
Write Data Width Specifies width of write data. 2^N bits are mapped to the WDATA port and the remaining bits, up to a maximum of 64, are mapped to WUSER port of the AXI4 Bus. N is an integer ranging from 3 to 10. The supported ranges for this parameter are from 8 to 192, 256 to 320, 512 to 576, and 1024 to 1088.
Read Data Width Specifies width of read data. 2^N bits are mapped to the RDATA port and the remaining bits, up to a maximum of 64, are mapped to RUSER port of the AXI4 Bus. N is an integer ranging from 3 to 10. The supported ranges for this parameter are from 8 to 192, 256 to 320, 512 to 576, and 1024 to 1088.
Use BUSER Use BUSER port on the AXI4 bus.
BUSER Width Specifies width of BUSER port of the AXI4 bus. The supported range for this parameter is from 1 to 64. Default value is 8.
Note: For more information on AXI signals, refer to the External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide or External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs, as appropriate, or to the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP User Guide.
Related Information
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