GTS Ethernet Intel® FPGA Hard IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817676
Date 4/07/2025
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

10.3.2. Verify the Simulation Results

The following sample output illustrates a successful simulation test run of the Dynamically Reconfigurable Mode in VCS* MX simulator. The script and waveform output is similar for other supported simulators.

The time now is 20000000000 

rck0_per = 6400.000000
rck0_per = 6400.000000
The time now is 30000000000 

---TX reset sequence completed -----
The time now is 40000000000 

---RX reset sequence completed -----
---IP_INST[0] Test  0;   ---Total 16 packets to send-----
---IP_INST[0] Start pkt gen TX-----
------Checking Packet TX/RX result-----
The time now is 50000000000 
------------  1 packets Sent;  0 packets Received--------
------------  16 packets Sent;  16 packets Received--------
------ALL   16  packets Sent out---
------ALL   16  packets Received---
------TX/RX packet check OK---

** Base Profile Testbench complete **
 
*****************************************
Info: "basic_avl_tb_top.sv", 321: basic_avl_tb_top: at time 54407351000 fs
Initial test of startup profile passed
Info: "basic_avl_tb_top.sv", 322: basic_avl_tb_top: at time 54407351000 fs
Starting DR sequence from FEC to no FEC
Info: "basic_avl_tb_top.sv", 323: basic_avl_tb_top: at time 54407351000 fs
Reset ETHs
Info: "basic_avl_tb_top.sv", 327: basic_avl_tb_top: at time 55407351000 fs
Waiting for reset ack
Info: "basic_avl_tb_top.sv", 329: basic_avl_tb_top: at time 55407351000 fs
Write from and to profile
Info: "basic_avl_tb_top.sv", 332: basic_avl_tb_top: at time 55488451000 fs
Trigger DR
Info: "basic_avl_tb_top.sv", 335: basic_avl_tb_top: at time 55572151000 fs
Wait for DR Ack....
DR_STATUS_L0: DR NIOS reconfiguration started 
DR_STATUS_L1: dr_load_Info: "basic_avl_tb_top.sv", 340: basic_avl_tb_top: at time 58548150000 fs
Wait for src grant....
sequence():
DR_STATUS_L1: dr_load_profile(): next_id=0x1, next_id_act=0 (1=Active 0=Neutral), init_startup=0
DR_STATUS_L2: dr_src_get_pause_grant(): ch_mask 0x1
Info: "basic_avl_tb_top.sv", 346: basic_avl_tb_top: at time 59413050000 fs
Wait for DR Config to be done....
DR_STATUS_L2: dr_src_get_pause_grant() done
DR_STATUS_L2: dr_onehot_mux_select_set(): profile_id=0, enable=0
DR_STATUS_L1: dr_load_ip_settings(): ch=0, ip_settings_ndx=0xThe time now is 60000000000 

25, num_ip_settings=4
DR_STATUS_L1: dr_load_ip_settings() done
DR_STATUS_L1: dr_load_ip_settings(): ch=0, ip_settings_ndx=0xe0, num_ip_settings=47


The time now is 210000000000 

DR_STATUS_L1: dr_load_ip_settings() done
DR_STATUS_L1: dr_load_profile() done (error = 0)
DR_STATUS_L1: dr_load_profile(): next_id=0x2, next_id_act=1 (1=Active 0=Neutral), init_startup=0
DR_STATUS_L1: dr_load_ip_settings(): ch=0, ip_settings_ndx=0x15b, num_ip_settings=43


The time now is 460000000000 

DR_STATUS_L1: drThe time now is 470000000000 

_load_ip_settings() done
DR_STATUS_L1: dr_load_ip_settings(): ch=0, ip_settings_ndx=0x20a, num_ip_settings=48


The time now is 610000000000 

DR_STATUS_L1: dr_load_ip_settings() done
DR_STATUS_L2: dr_onehot_mux_select_set(): profile_id=1, enable=1
DR_STATUS_L1: dr_load_profile() done (error = 0)
DR_STATUS_L2: dr_src_release_pause_request(): 0x1
Info: "basic_avl_tb_top.sv", 348: basic_avl_tb_top: at time 616166850000 fs
Waiting for reset ack
Info: "basic_avl_tb_top.sv", 350: basic_avl_tb_top: at time 616166850000 fs
Reset ack asserted
Info: "basic_avl_tb_top.sv", 351: basic_avl_tb_top: at time 616166850000 fs
Deassert reset of ETHs
DR_STATUS_L2: dr_src_release_pause_request() done
DR_STATUS_L1: dr_load_sequence() done, iteration to final profile successfully finish (iter=3)
DR_STATUS_L0: DR NIOS reconfiguration done
DR_STATUS_L0: DR NIOS readInfo: "basic_avl_tb_top.sv", 356: basic_avl_tb_top: at time 617166850000 fs
Check error status
y for next trigger
DR_STATUS_====>MATCH!  Read addr = 00000070, ReaddataValid = 1 Readdata = 00000001 Expected_Readdata = 00000001 

L0: DR NIOS waiting for trigge====>MATCH!  Read addr = 00000074, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 


Info: "basic_avl_tb_top.sv", 365: basic_avl_tb_top: at time 617487451000 fs
DR Controller state: 5
Info: "basic_avl_tb_top.sv", 367: basic_avl_tb_top: at time 617487451000 fs
Writing into SIP MRIP reg
Info: "basic_avl_tb_top.sv", 373: basic_avl_tb_top: at time 617589751000 fs
Waiting for TX ready 
The time now is 620000000000 

rck0_per = 6400.000000
The time now is 630000000000 

rck0_per = 6400.000000
The time now is 640000000000 

Info: "basic_avl_tb_top.sv", 376: basic_avl_tb_top: at time 643602535000 fs
ETH Tx ready
The time now is 650000000000 


Info: "basic_avl_tb_top.sv", 378: basic_avl_tb_top: at time 664256307000 fs
ETH RX ready
The time now is 670000000000 

Info: "basic_avl_tb_top.sv", 385: basic_avl_tb_top: at time 675184650000 fs
 ************* Secondary Profile Packet transaction started *********....
---IP_INST[0] Test  0;   ---Total 16 packets to send-----
The time now is 680000000000 

------IP_INST[0] Start pkt gen TX-----
------Checking Packet TX/RX result-----
------------   3 packets Sent;    0 packets Received--------
------------  16 packets Sent;    16 packets Received--------
------ALL 16 packets Sent out---
------ALL 16 packets Received---
------TX/RX packet check OK---

**Secondary Profile Testbench complete
*****************************************
Note: The MAC Avalon® -ST client interface uses registers 0x50030 and 0x50000, only applicable to this interface. You can ignore any errors from these registers in other client interface modes.