GTS Ethernet Intel® FPGA Hard IP User Guide: Agilex™ 5 FPGAs and SoCs

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Date 4/07/2025
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Install and License the GTS Ethernet Intel® FPGA Hard IP 3. Configure and Generate Ethernet Hard IP variant 4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application 5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance 6. Simulate, Compile, and Validate (MII PCS Only/PCS66 OTN/PCS66 FlexE) - Single Instance 7. Simulate, Compile, and Validate SyncE - Single Instance 8. Simulate and Compile PTP1588 - Single Instance 9. Simulate, Compile, and Validate - Multiple Instance 10. Simulate, Compile, and Validate (Dynamically Reconfigurable Ethernet Mode – MAC) 11. Simulate, Compile, and Validate - Auto-Negotiation and Link Training 12. Troubleshoot and Diagnose Issues 13. Appendix A: Functional Description 14. Appendix B: Configuration Registers 15. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide: Agilex™ 5 FPGAs and SoCs
1. Overview x
1.1. Release Information 1.2. High-Level Functional Overview 1.3. Acronyms 1.4. Agilex® 5 Ethernet Portfolio and Target Applications 1.5. Agilex® 5 Ethernet Hard IP Features 1.6. GTS Ethernet Intel® FPGA Hard IP Design Flow
1.5. Agilex® 5 Ethernet Hard IP Features x
1.5.1. Device Family Support 1.5.2. Device Speed Grade Support 1.5.3. Resource Utilization 1.5.4. Round-Trip Latency
3. Configure and Generate Ethernet Hard IP variant x
3.1. Create Quartus Project 3.2. Configure GTS Ethernet Hard IP 3.3. Generate HDL for Synthesis and Simulation 3.4. Generated File Structure 3.5. Generate GTS EHIP Design Example 3.6. Analog Parameter Options
3.5. Generate GTS EHIP Design Example x
3.5.1. Directory Structure
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application x
4.1. Implement Required Clocking 4.2. Implement Required Resets 4.3. Connect the Status Interface 4.4. Connect the MAC Avalon Streaming Client Interface 4.5. Connect the MII PCS Only Client Interface 4.6. Connect the PCS66 Client Interface – FlexE and OTN 4.7. Connect the Precision Time Protocol Interface 4.8. Connect the Ethernet Hard IP Reconfiguration Interface 4.9. Connect the Auto-Negotiation and Link Training 4.10. Connect the Multirate Auto-Negotiation and Link Training 4.11. Connect the Dynamically Reconfigurable Ethernet Mode
4.1. Implement Required Clocking x
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance 4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances 4.1.3. Implement Clock Connections to MAC Asynchronous Operation 4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E) 4.1.5. Implement Clock Connections in PTP-Based Design
4.2. Implement Required Resets x
4.2.1. Reset Sequence 4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP
4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP x
4.2.2.1. Requirements and Considerations for GTS Reset Sequencer Intel® FPGA IP
4.3. Connect the Status Interface x
4.3.1. Use i_stats_snapshot to Read Stats Counters
4.4. Connect the MAC Avalon Streaming Client Interface x
4.4.1. Connect the TX MAC Avalon Streaming Client Interface 4.4.2. Connect the RX MAC Avalon Streaming Client Interface 4.4.3. Connect the MAC Flow Control Interface
4.4.1. Connect the TX MAC Avalon Streaming Client Interface x
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough 4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough 4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion 4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2. Connect the RX MAC Avalon Streaming Client Interface x
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled 4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled 4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled 4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
4.4.3. Connect the MAC Flow Control Interface x
4.4.3.1. Connect the TX MAC Flow Control Interface 4.4.3.2. Connect the RX MAC Flow Control Interface
4.5. Connect the MII PCS Only Client Interface x
4.5.1. Connect the MII PCS Mode TX Interface 4.5.2. Connect the MII PCS Mode RX Interface
4.5.1. Connect the MII PCS Mode TX Interface x
4.5.1.1. Insert Alignment Marker
4.5.2. Connect the MII PCS Mode RX Interface x
4.5.2.1. Receive Alignment Marker
4.6. Connect the PCS66 Client Interface – FlexE and OTN x
4.6.1. Connect the FlexE and OTN Mode TX Interface 4.6.2. Connect the FlexE and OTN Mode RX Interface
4.6.1. Connect the FlexE and OTN Mode TX Interface x
4.6.1.1. Insert Alignment Marker
4.6.2. Connect the FlexE and OTN Mode RX Interface x
4.6.2.1. Receive Alignment Marker
4.7. Connect the Precision Time Protocol Interface x
4.7.1. Connect the Time-of-Day Interface 4.7.2. Connect the TX Two-Step Timestamp Interface 4.7.3. Connect the TX One-Step Timestamp Interface 4.7.4. Connect the RX Timestamp Interface 4.7.5. Connect the PTP Status Interface
4.7.3. Connect the TX One-Step Timestamp Interface x
4.7.3.1. PTP Field Offset for 1-Step Operation
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance x
5.1. Design Example Features 5.2. Design Example Components 5.3. Simulate the Design Example 5.4. Compile the Design Example 5.5. Validate the Design Example
5.3. Simulate the Design Example x
5.3.1. Simulation Testbench Flow 5.3.2. Verify the Simulation Results
5.5. Validate the Design Example x
5.5.1. Configure the Clocks in Hardware 5.5.2. Program the FPGA 5.5.3. Run the Hardware Test
6. Simulate, Compile, and Validate (MII PCS Only/PCS66 OTN/PCS66 FlexE) - Single Instance x
6.1. Design Example Features 6.2. Design Example Components 6.3. Simulate the Design Example 6.4. Compile the Design Example 6.5. Validate the Design Example
6.3. Simulate the Design Example x
6.3.1. Simulation Testbench Flow 6.3.2. Simulators Output
6.5. Validate the Design Example x
6.5.1. Configure the Clocks in Hardware 6.5.2. Program the FPGA 6.5.3. Run the Hardware Test
7. Simulate, Compile, and Validate SyncE - Single Instance x
7.1. Design Example Features 7.2. Design Example Components 7.3. Simulate the Design Example 7.4. Compile the Design Example 7.5. Validate the Design Example
7.3. Simulate the Design Example x
7.3.1. Simulation Testbench Flow for Single Instance with SyncE 7.3.2. Simulator Output
7.5. Validate the Design Example x
7.5.1. Configure the Clocks in Hardware 7.5.2. Program the FPGA 7.5.3. Run the Hardware Test
8. Simulate and Compile PTP1588 - Single Instance x
8.1. Design Example Features 8.2. Design Example Components 8.3. Simulate the Design Example 8.4. Compile the Design Example 8.5. Validate the Design Example
8.3. Simulate the Design Example x
8.3.1. Simulation Testbench Flow 8.3.2. Simulator Output
8.5. Validate the Design Example x
8.5.1. Configure the Clocks in Hardware 8.5.2. Program the FPGA 8.5.3. Run the Hardware Test
9. Simulate, Compile, and Validate - Multiple Instance x
9.1. Design Example Features 9.2. Design Example Components 9.3. Simulate the Design Example 9.4. Compile the Design Example 9.5. Validate the Design Example
9.3. Simulate the Design Example x
9.3.1. Simulation Testbench Flow for MAC Mode 9.3.2. Simulator Output
9.5. Validate the Design Example x
9.5.1. Configure the Clocks in Hardware 9.5.2. Program the FPGA 9.5.3. Run the Hardware Test
10. Simulate, Compile, and Validate (Dynamically Reconfigurable Ethernet Mode – MAC) x
10.1. Design Example Features 10.2. Design Example Components 10.3. Simulate the Design Example 10.4. Compile the Design Example 10.5. Validate the Design Example
10.3. Simulate the Design Example x
10.3.1. Simulation Testbench Flow 10.3.2. Verify the Simulation Results
10.5. Validate the Design Example x
10.5.1. Configure the Clocks in Hardware 10.5.2. Program the FPGA 10.5.3. Run the Hardware Test
11. Simulate, Compile, and Validate - Auto-Negotiation and Link Training x
11.1. Auto-Negotiation and Link Training for General Ethernet Mode 11.2. Multirate Auto-Negotiation and Link Training for Reconfigurable Mode AN/LT 11.3. Design Example Features 11.4. Design Example Components 11.5. Simulate the Design Example 11.6. Compile the Design Example 11.7. Validate the Design Example
11.5. Simulate the Design Example x
11.5.1. Simulation Testbench Flow 11.5.2. Simulation Output
11.7. Validate the Design Example x
11.7.1. Configure the Clocks in Hardware 11.7.2. Program the FPGA 11.7.3. Run the Hardware Test
12. Troubleshoot and Diagnose Issues x
12.1. Enable Diagnostic Lookback Modes 12.2. Troubleshoot the Reset Sequence 12.3. Use Signal Tap Analyzer for Troubleshooting
12.1. Enable Diagnostic Lookback Modes x
12.1.1. Internal Serial Loopback 12.1.2. Enable MAC Loopback 12.1.3. Enable PCS Loopback 12.1.4. Enable External Loopback 12.1.5. Packet Client Loopback
12.2. Troubleshoot the Reset Sequence x
12.2.1. Debug the Power Up Reset Sequence 12.2.2. Debug the TX Reset Entry Sequence 12.2.3. Debug the TX Reset Exit Sequence 12.2.4. Debug the RX Reset Entry Sequence 12.2.5. Debug the RX Reset Exit Sequence 12.2.6. Debug the Auto Recovery Reset Sequence
13. Appendix A: Functional Description x
13.1. Datapath Description 13.2. GTS Ethernet Intel® FPGA Hard IP MAC 13.3. PCS, OTN, and FlexE Modes 13.4. Precision Time Protocol Interface 13.5. Auto-Negotiation and Link Training
13.2. GTS Ethernet Intel® FPGA Hard IP MAC x
13.2.1. MAC TX Datapath 13.2.2. MAC RX Datapath 13.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 13.2.4. Link Fault Signaling 13.2.5. Order of Ethernet Transmission:
13.2.1. MAC TX Datapath x
13.2.1.1. Insert TX Preamble, Start, and SFD 13.2.1.2. Insert Source Address 13.2.1.3. Process Length/Type Field 13.2.1.4. Pad the Client Frame 13.2.1.5. Insert Frame Check Sequence (CRC-32) 13.2.1.6. Generate and Insert Inter-Packet Gap
13.2.2. MAC RX Datapath x
13.2.2.1. Process RX Preamble 13.2.2.2. Check RX Strict SFD 13.2.2.3. Check RX FCS 13.2.2.4. Handle RX Malformed Packet 13.2.2.5. Remove PAD Bytes and FCS Bytes from RX Frames 13.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 13.2.2.7. Inter-Packet Gap
13.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
13.2.3.1. Conditions Triggering XOFF Frame Transmission 13.2.3.2. Conditions Triggering XON Frame Transmission 13.2.3.3. Pause Control and Generation Interface 13.2.3.4. Pause Control Frame Filtering
13.3. PCS, OTN, and FlexE Modes x
13.3.1. PCS Mode 13.3.2. OTN Mode 13.3.3. FlexE Mode
13.4. Precision Time Protocol Interface x
13.4.1. Features 13.4.2. PTP User Flow 13.4.3. Make PTP UI Adjustments 13.4.4. Reference Time Interval 13.4.5. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware)
13.4.2. PTP User Flow x
13.4.2.1. PTP TX User Flow 13.4.2.2. PTP RX User Flow
13.4.3. Make PTP UI Adjustments x
13.4.3.1. Adjust TX UI 13.4.3.2. Adjust RX UI
14. Appendix B: Configuration Registers x
14.1. Ethernet Avalon® Memory-Mapped Interface Address Space 14.2. Packet Client Registers
1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only/PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate (Dynamically Reconfigurable Ethernet Mode – MAC)
11. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
12. Troubleshoot and Diagnose Issues
13. Appendix A: Functional Description
14. Appendix B: Configuration Registers
15. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide: Agilex™ 5 FPGAs and SoCs

4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP

Instantiate and connect the GTS Reset Sequencer Intel® FPGA IP to the GTS Ethernet Intel® FPGA Hard IP . The following subsections describe this process:

The GTS Reset Sequencer Intel® FPGA IP receives reset requests from the GTS Ethernet Intel® FPGA Hard IP and grants them based on priority.

Figure 25. Connect to the GTS Reset Sequencer Intel® FPGA IP
The following table describes the input and output signals of the GTS Reset Sequencer Intel® FPGA IP:
Table 24.  GTS Reset Sequencer Intel® FPGA IP Signals
  • N: Number of channels used.
  • M: Number of banks per side of the device.
Signal Name Width Description
i_src_rs_req N Request from EHIP to GTS Reset Sequencer Intel® FPGA IP to perform a reset of the target transceiver channel.
i_src_rs_priority N

Binary priority input

  • 0 - Low priority
  • 1 - High priority

This port is used to set priority for a channel that you need to prioritize the reset sequence when there are multiple channels being reset simultaneously. You must tie the input to 0 except for the priority channel which needs to be set to 1.

o_src_rs_grant N Grant from GTS Reset Sequence Intel® FPGA IP to EHIP. Asserts when the Reset Sequencer acknowledges the reset request.
o_pma_cu_clk M PMA Control Unit clock output, one per GTS bank for each side of the device. This clock port must be connected as shown in the Connect to the GTS Reset Sequencer Intel® FPGA IP .
i_refclk_bus_out 1 Input of the GTS Reset Sequencer Intel FPGA IP. It indicates the failure of the local or regional reference clock at the left or right transceiver banks.
o_shoreline_refclk_fail_stat 1 Reference clock fail status indication from GTS Reset Sequencer Intel FPGA IP to user logic.

Refer to Input Reference Clock Buffer Protection and Implementing the Reset Sequencer Intel® FPGA IP of the GTS Transceiver PHY User Guide for more functional details on i_refclk_bus_out signal.


Section Content
Requirements and Considerations for GTS Reset Sequencer Intel FPGA IP

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