F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

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ID 815243
Date 5/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile Low Latency 100G Ethernet Design Example Description 3. F-Tile Low Latency 100G Ethernet Intel FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Generating Tile Files 1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile Low Latency 100G Ethernet Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing 2.7. Design Example Registers 2.8. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
1. Quick Start Guide
2. F-Tile Low Latency 100G Ethernet Design Example Description
3. F-Tile Low Latency 100G Ethernet Intel FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

2.4.2. Simulation Design Example Components

The testbench sends traffic through the IP, exercising the transmit side and receive side of the IP.

The simulation design example top-level test file is basic_avl_tb_top.sv. This file provides a clock reference clk_ref of 156.25 MHz to the PHY. It includes a task to send and receive 10 packets.

Table 6.  Testbench File Descriptions

File Names

Description

Key Testbench and Simulation Files

basic_avl_tb_top.v Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.

Testbench Scripts

run_vsim.do

The QuestaSim* script to run the testbench.

run_vcs.sh

The VCS* script to run the testbench.

run_vcsmx.sh

The VCS* MX script (combined Verilog HDL and SystemVerilog with VHDL) to run the testbench.

run_xcelium.sh The Xcelium* script to run the testbench.
run_riviera.do The Riviera-PRO* script to run the testbench.
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