Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide

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ID 814028
Date 6/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Product Family Plan 3. Package Information 4. Thermal Design Considerations 5. Pin Connection Guidelines and Pinouts 6. Printed Circuit Board (PCB) Design 7. Signal Integrity Simulations 8. Validation 9. Document Revision History for the Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide
1. Introduction x
1.1. Status Definitions 1.2. Notifications 1.3. Secure Asset Access—Developer Zone Premium (DZP)
2. Product Family Plan x
2.1. Product Table Information 2.2. Part Number Decoder 2.3. Series/Package/Tile Comparison Table 2.4. Migration within a Package 2.5. Series Package Options Versus Tiles—Support I/O Counts 2.6. Package Comparison Tables
2.5. Series Package Options Versus Tiles—Support I/O Counts x
2.5.1. Agilex™ 7 F-Series Devices with F-Tiles 2.5.2. Agilex™ 7 F-Series Devices with E-Tile and P-Tiles 2.5.3. Agilex™ 7 I-Series Devices with F-Tiles 2.5.4. Agilex™ 7 I-Series Devices with F-Tiles and R-Tiles 2.5.5. Agilex™ 7 M-Series Devices with HBM2e 2.5.6. Agilex™ 7 M-Series Devices without HBM2e
3. Package Information x
3.1. Ball Grid Array (BGA) Package
3.1. Ball Grid Array (BGA) Package x
3.1.1. Package Mechanical Drawings 3.1.2. Package Ball Coordinates 3.1.3. Package PCB Footprints 3.1.4. Land Pattern PCB Design Recommendations (MAS)
4. Thermal Design Considerations x
4.1. Power Estimation and Analysis Tools 4.2. Compact Thermal Models (CTM) 4.3. Heat Sink 4.4. Remote Temperature Sensing using Temperature Sensing Diodes (TSDs)
4.1. Power Estimation and Analysis Tools x
4.1.1. Intel® FPGA Power and Thermal Calculator (PTC) 4.1.2. Quartus® Prime Power Analyzer (QPA)
4.3. Heat Sink x
4.3.1. Heat Sink Rework
5. Pin Connection Guidelines and Pinouts x
5.1. Pin Connection Guidelines 5.2. Pinout Introduction 5.3. I/O Banks 5.4. Transceivers 5.5. Validating Pins
5.2. Pinout Introduction x
5.2.1. F-Series Pinouts 5.2.2. I-Series Pinouts 5.2.3. M-Series Pinouts 5.2.4. Hard Processor System (HPS) Pin Information 5.2.5. External Memory Interface (EMIF) Pin Information
5.3. I/O Banks x
5.3.1. Types of Banks 5.3.2. Bank Locations 5.3.3. Selecting Bank Usage
5.3.1. Types of Banks x
5.3.1.1. General-purpose I/O (GPIO) 5.3.1.2. Secure Device Manager (SDM) I/O 5.3.1.3. Hard Processor System (HPS) I/O
5.3.3. Selecting Bank Usage x
5.3.3.1. Agilex™ 7 M-Series FPGA I/O Placement
6. Printed Circuit Board (PCB) Design x
6.1. Schematic Symbols 6.2. Power Supply 6.3. External Memory 6.4. Transceivers 6.5. SoC FPGA Hard Processor Systems (HPS) 6.6. JTAG Interface 6.7. FPGA Configuration 6.8. Development Kit Examples 6.9. Schematic Review Worksheet 6.10. Step-by-Step Generic PCB Design Flow
6.4. Transceivers x
6.4.1. High-Speed Serial Interface Signal Integrity Design Guidelines 6.4.2. Tiles
6.4.2. Tiles x
6.4.2.1. F-Tile Transceivers 6.4.2.2. E-Tile Transceivers 6.4.2.3. P-Tile Transceivers 6.4.2.4. R-Tile Transceivers
6.10. Step-by-Step Generic PCB Design Flow x
6.10.1. Getting Ready 6.10.2. Schematic Design 6.10.3. Board Layout 6.10.4. Checks
7. Signal Integrity Simulations x
7.1. Intel Advanced Link Analyzer 7.2. Signal Integrity Analysis with Third-Party Tools 7.3. IBIS Models 7.4. Transceiver IBIS-AMI Models 7.5. Net Length Reports
8. Validation x
8.1. Validation and Debug Tools 8.2. Boundary-Scan Description Language (BSDL) Models
8.1. Validation and Debug Tools x
8.1.1. Transceiver Toolkit 8.1.2. EMIF Toolkit and Debug Tools 8.1.3. System Console 8.1.4. Signal Tap 8.1.5. Programmer’s Configuration Debugger Tool
8.2. Boundary-Scan Description Language (BSDL) Models x
8.2.1. Pre-Configuration BSDL Files 8.2.2. Post-Configuration BSDL Generator
1. Introduction
2. Product Family Plan
3. Package Information
4. Thermal Design Considerations
5. Pin Connection Guidelines and Pinouts
6. Printed Circuit Board (PCB) Design
7. Signal Integrity Simulations
8. Validation
9. Document Revision History for the Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide

2.6. Package Comparison Tables

The following tables highlight package size, area, height, pitch, pattern, and referenced package mechanical drawing numbers for the different packages offered.

Devices with the common package code are footprint compatible. The Top Hat (Lid Step) and overall height may vary per package/density option as they are optimized for the corresponding device and its construction. Also, note the Top Hat size for heat sink considerations. Consult the package mechanical drawing for the package height. Height numbers in following table are pre surface mounting. All dimensions are nominal values.

Table 10.  F-Series BGA Package Table
Package Code Ball Count Size (mm x mm) Area (mm2) Height (mm) Pitch (mm) Pattern Applicable Devices Drawing No.
R16A 1546 37.5 x 34 1,275 3.529 0.92 Hex AGF 006/008 M61689
R24C 2340 45 x 42 1,890 3.529 0.92 Hex AGF 006/008 M67981
AGF 012/014 M63529
AGF 019/023 M74495
AGF 022/027 M71938
R24D 2340 45 x 42 1,890 3.529 0.92 Hex AGF 006/008 M67981
AGF 012/014 M63529
R24B 2486 55 x 42.5 2,338 3.56 1 Hex AGF 012/014 K90452
R25A 4 2581 52.5 x 40.5 2,126 3.529 0.92/0.94 Hex AGF 019/023 M49645
3.689 AGF 022/027 M15694
R31C 3184 56 x 45 2,520 3.53 0.92 Hex AGF 019/023 M79040
AGF 022/027 M72657
Table 11.  I-Series BGA Package Table
Package Code Ball Count Size (mm x mm) Area (mm2) Height (mm) Pitch (mm) Pattern Applicable Devices Drawing No.
R18A 1805 42.5 x 42.5 1,806 3.56 1.025 Hex AGI 019/023 M67999
R29A 2957 56 x 45 2,520 3.529 0.92/1.0 Hex AGI 022/027 M72329
R29D AGI 041 M97423
R31A 3184 56 x 45 2,520 3.529 0.92 Hex AGI 022/027 M97215
R31B 3184 56 x 45 2,520 3.529 0.92 Hex AGI 019/023 M79040
AGI 022/027 M72657
AGI 041 N21348
R39A 3948 56 x 56 3,136 3.999 0.92 Hex AGI 035/040 M68002
Table 12.  M-Series BGA Package Table
Package Code Ball Count Size (mm x mm) Area (mm2) Height (mm) Pitch (mm) Pattern Applicable Devices Drawing No.
R31B 3184 56 x 45 2,520 4.725 0.92 Hex AGM 032/039 N39401
R47A 4700 56 x 66 3,696 4.875 0.92 Hex AGM 032/039 N33898
R47B 4700 56 x 66 3,696 4.875 0.92 Hex AGM 032/039 N40107
4 For the R25A package, height depends upon the device density. This may have dependencies upon the heat sink implementation. This package also uses two pad pitches depending upon the region of the BGA.
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