GTS Serial Lite IV Intel® FPGA IP User Guide

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ID 813966
Date 8/14/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Serial Lite IV Intel® FPGA IP User Guide: Agilex™ 5 E-Series/D-Series and Agilex™ 3 Devices 2. GTS Serial Lite IV Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. Parameters 6. GTS Serial Lite IV Intel® FPGA IP Interface Signals 7. Designing with GTS Serial Lite IV Intel® FPGA IP 8. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP User Guide
2. GTS Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Parameters and Options 3.3. Generated File Structure 3.4. Simulating Intel® FPGA IP Cores 3.5. Synthesizing IP Cores in Other EDA Tools 3.6. Compiling the Full Design
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Altera FPGA IP Evaluation Mode
3.4. Simulating Intel® FPGA IP Cores x
3.4.1. Simulating and Verifying the Design
4. Functional Description x
4.1. TX Datapath 4.2. RX Datapath 4.3. GTS Serial Lite IV Intel® FPGA IP Clock Architecture 4.4. Reset and Link Initialization 4.5. Link Rate and Bandwidth Efficiency Calculation
4.1. TX Datapath x
4.1.1. TX MAC Adapter 4.1.2. Control Word (CW) Insertion 4.1.3. TX CRC 4.1.4. TX MII Encoder 4.1.5. TX PCS and PMA
4.1.2. Control Word (CW) Insertion x
4.1.2.1. Start-of-burst CW 4.1.2.2. End-of-burst CW 4.1.2.3. Alignment Paired CW 4.1.2.4. Empty-cycle CW 4.1.2.5. Idle CW 4.1.2.6. Data Word
4.2. RX Datapath x
4.2.1. RX PCS and PMA 4.2.2. RX MII Decoder 4.2.3. RX CRC 4.2.4. RX Deskew 4.2.5. RX CW Removal
4.4. Reset and Link Initialization x
4.4.1. TX Reset and Initialization Sequence 4.4.2. RX Reset and Initialization Sequence
6. GTS Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA/PCS Signals
7. Designing with GTS Serial Lite IV Intel® FPGA IP x
7.1. Reset Guidelines 7.2. Error Handling Guidelines 7.3. Analog Parameter Settings
1. About the GTS Serial Lite IV Intel® FPGA IP User Guide: Agilex™ 5 E-Series/D-Series and Agilex™ 3 Devices
2. GTS Serial Lite IV Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Parameters
6. GTS Serial Lite IV Intel® FPGA IP Interface Signals
7. Designing with GTS Serial Lite IV Intel® FPGA IP
8. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP User Guide

5. Parameters

Table 18.   GTS Serial Lite IV Intel® FPGA IP Parameter Description
Parameter Value Default Description
General Design Options
PMA data rate 1 Gbps – 28.1 Gbps 10.3125 Gbps Specifies the effective data rate at the output of the transceiver incorporating transmission and other overheads. The value is calculated by the IP by rounding up to 1 decimal place in Gbps unit.
  • Supported rates for Agilex™ 5 E-Series (Device Group B): 1 - 17.16 Gbps.
  • Supported rates for Agilex™ 5 E-Series (Device Group A) and D-Series: 1 - 28.1 Gbps.
  • Supported rates for Agilex™ 3: 1 - 12.5 Gbps.
PMA mode
  • Duplex, Tx and Rx
 Duplex The supported direction is duplex, Tx and Rx.
Number of PMA lanes 1 – 4 1 Select the number of lanes. The supported number of lanes is 1 – 4.
PMA reference clock frequency 100 MHz – 379.84375 MHz, depending on the selected transceiver data rate. 156.25 MHz Specifies the reference clock frequency of the transceiver.
System PLL reference clock frequency — 170 MHz Available when the System PLL frequency selection is set to Custom, regardless of the transceiver type.
System PLL frequency
  • N 9
  • Custom
 322.265625 MHz Specifies the system PLL clock frequency.
Custom System PLL frequency — 322.265625 MHz

Specifies custom system PLL frequency. This field is enabled when System PLL frequency is set to Custom.

When RS-FEC enabled, the maximum custom system PLL frequency allowed is 1.4 x 2 x (PMA data rate/64).
Alignment Period 128 – 65536 128 Specifies the alignment marker period.

The value must be x2.
Enable RS-FEC

Enable

Disable

 Disable Turn on to enable the RS-FEC (528, 514) feature.
User Interface
Streaming mode
  • FULL
  • BASIC
 Full Select the data streaming for the IP.

FULL: This mode sends a start-of-packet and end-of-packet cycle within a frame.

BASIC: This is a pure streaming mode where data is sent without a start-of-packet, empty, and end-of-packet to increase bandwidth.
Enable CRC

Enable

Disable

 Disable Turn on to enable CRC error detection and correction.
Enable auto alignment

Enable

Disable

 Disable Turn on to enable automatic lane alignment feature.
Enable debug endpoint

Enable

Disable

 Disable Turn on to enable debug endpoint for Transceiver Toolkit.
Dual Simplex (This parameter setting is only available when you set PMA mode as Tx or Rx.)
RS-FEC enabled on the other Serial Lite IV Simplex IP placed at the same channel(s) for dual simplex

Enable

Disable

 Disable

RS-FEC option on the other Serial Lite IV Simplex IP that will be placed on the same channel(s) for dual simplex.

Turn on this option if you require a configuration of both RS-FEC enabled for GTS Serial Lite IV IPs in a dual simplex design, where both TX and RX are placed on the same channel(s).
Note: To support RS-FEC in a dual simplex design, you must meet the following requirements:
  • Both simplex Tx and simplex Rx IPs enabled this parameter
  • Both simplex Tx and simplex Rx IPs enabled RS-FEC
  • Both simplex Tx and simplex Rx IPs have the same number of PMA lanes
  • Both Simplex Tx and simplex Rx IPs share the same source for the sys_clk signal
9 This is a system-generated value based on the PMA data rate.
Level Two Title