GTS Serial Lite IV Intel® FPGA IP User Guide

ID 813966
Date 4/01/2024
Public

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4.1.4. TX MII Encoder

The TX MII encoder handles the packet transmission from the MAC to the TX PCS.

The following table demonstrates the TX MII data pattern.

Table 16.  TX MII Data Pattern
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
SOP_CW DATA_1 DATA_2 DATA_3 EOP_CW