GTS Serial Lite IV Intel® FPGA IP User Guide

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ID 813966
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. About the GTS Serial Lite IV Intel® FPGA IP User Guide: Agilex™ 5 E-Series Devices 2. GTS Serial Lite IV Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. Parameters 6. GTS Serial Lite IV Intel® FPGA IP Interface Signals 7. Designing with GTS Serial Lite IV Intel® FPGA IP 8. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP User Guide
2. GTS Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Parameters and Options 3.3. Generated File Structure 3.4. Simulating Intel® FPGA IP Cores 3.5. Synthesizing IP Cores in Other EDA Tools 3.6. Compiling the Full Design
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.4. Simulating Intel® FPGA IP Cores x
3.4.1. Simulating and Verifying the Design
4. Functional Description x
4.1. TX Datapath 4.2. RX Datapath 4.3. GTS Serial Lite IV Intel® FPGA IP Clock Architecture 4.4. Reset and Link Initialization 4.5. Link Rate and Bandwidth Efficiency Calculation
4.1. TX Datapath x
4.1.1. TX MAC Adapter 4.1.2. Control Word (CW) Insertion 4.1.3. TX CRC 4.1.4. TX MII Encoder 4.1.5. TX PCS and PMA
4.1.2. Control Word (CW) Insertion x
4.1.2.1. Start-of-burst CW 4.1.2.2. End-of-burst CW 4.1.2.3. Alignment Paired CW 4.1.2.4. Empty-cycle CW 4.1.2.5. Idle CW 4.1.2.6. Data Word
4.2. RX Datapath x
4.2.1. RX PCS and PMA 4.2.2. RX MII Decoder 4.2.3. RX CRC 4.2.4. RX Deskew 4.2.5. RX CW Removal
4.4. Reset and Link Initialization x
4.4.1. TX Reset and Initialization Sequence 4.4.2. RX Reset and Initialization Sequence
6. GTS Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA/PCS Signals
7. Designing with GTS Serial Lite IV Intel® FPGA IP x
7.1. Reset Guidelines 7.2. Error Handling Guidelines 7.3. Analog Parameter Settings
1. About the GTS Serial Lite IV Intel® FPGA IP User Guide: Agilex™ 5 E-Series Devices
2. GTS Serial Lite IV Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Parameters
6. GTS Serial Lite IV Intel® FPGA IP Interface Signals
7. Designing with GTS Serial Lite IV Intel® FPGA IP
8. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP User Guide

2.6. Bandwidth Efficiency

Table 6.  Bandwidth Efficiency
Variables Settings
Transceiver mode NRZ
Streaming mode Full Basic
RS-FEC Disabled Disabled
Serial interface bit rate in Gbps (RAW_RATE) 10.3125 10.3125
Burst size of a transfer in number of word (BURST_SIZE) 1 2,048 4,194,304
Alignment period in clock cycle (SRL4_ALIGN_PERIOD) 4,096 4,096
64/66b encode 0.96969697 0.96969697
Overhead of a burst size in number of word (BURST_SIZE_OVHD) 2 2 0 3
Alignment marker period in clock cycle (ALIGN_MARKER_PERIOD) 81,916 81,916
Alignment marker width in clock cycle (ALIGN_MARKER_WIDTH) 0 0
Bandwidth efficiency 4 0.96827698 0.96922348
Effective rate (Gbps) 5 9.98535635625 9.9951171375
Maximum user clock frequency (MHz) 6 156.02119306640625 156.1737052734375
Related Information
1 The BURST_SIZE for Basic mode approaches infinity, hence a large number is used.
2 In Full mode, the BURST_SIZE_OVHD size is inclusive of the START/END paired Control Words in a data stream.
3 For Basic mode, BURST_SIZE_OVHD is 0 because there is no START/END during streaming.
4 Refer to Link Rate and Bandwidth Efficiency Calculation for bandwidth efficiency calculation.
5 Refer to Link Rate and Bandwidth Efficiency Calculation for effective rate calculation.
6 Refer to Link Rate and Bandwidth Efficiency Calculation for maximum user clock frequency calculation.
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