Visible to Intel only — GUID: tnj1701168737614
Ixiasoft
Visible to Intel only — GUID: tnj1701168737614
Ixiasoft
3.4.1. Simulating and Verifying the Design
By default, the parameter editor generates simulator-specific scripts containing commands to compile, elaborate, and simulate Intel FPGA IP models and simulation model library files. You can copy the commands into your simulation testbench script, or edit these files to add commands for compiling, elaborating, and simulating your design and testbench.
Simulator |
File Directory |
Script |
---|---|---|
ModelSim* | <variation name> /sim/mentor |
msim_setup.tcl 7 |
QuestaSim* | ||
VCS* | <variation name> /sim/synopsys/vcs |
vcs_setup.sh |
VCS* MX | <variation name> /sim/synopsys/vcsmx |
vcsmx_setup.sh synopsys_sim.setup |