6.3. MAC Signals
Name | Width | Direction | Clock Domain | Description |
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tx_avs_ready | 1 | Output | tx_core_clkout | Avalon® streaming signal. When asserted, indicates that the TX MAC is ready to accept data. |
tx_avs_data |
64*N | Input | tx_core_clkout | Avalon® streaming signal. TX data. |
tx_avs_channel | 8 | Input | tx_core_clkout | Avalon® streaming signal. The channel number for data being transferred on the current cycle. This signal is not available in Basic mode. |
tx_avs_valid | 1 | Input | tx_core_clkout | Avalon® streaming signal. When asserted, indicates the TX data signal is valid. |
tx_avs_startofpacket | 1 | Input | tx_core_clkout | Avalon® streaming signal. When asserted, indicates the start of a TX data packet. Assert for only a single clock cycle for each packet. This signal is not available in Basic mode. |
tx_avs_endofpacket | 1 | Input | tx_core_clkout | Avalon® streaming signal. When asserted, indicates the end of a TX data packet. Assert for only a single clock cycle for each packet. This signal is not available in Basic mode. |
tx_avs_empty | 5 | Input | tx_core_clkout | Avalon® streaming signal. Indicates the number of non-valid words in the final burst of the TX data. This signal is not available in Basic mode.
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tx_num_valid_bytes_eob | 4 | Input | tx_core_clkout | Indicates the number of valid bytes in the last word of the final burst. This signal is not available in Basic mode. |
tx_is_usr_cmd | 1 | Input | tx_core_clkout | When asserted, this signal initiate a user-defined information cycle. Assert this signal at the same clock cycle as tx_startofpacket assertion. This signal is not available in Basic mode. |
tx_link_up | 1 | Output | tx_core_clkout | When asserted, indicates the TX data link is ready for data transmission. |
tx_link_reinit | 1 | Input | tx_core_clkout | When asserted, this signal initiates lanes re-alignment. Assert this signal for one clock cycle to trigger the MAC to send ALIGN CW. |
crc_error_inject | N | Input | tx_core_clkout | When asserted, the MAC injects a CRC32 error to selected lanes. |
tx_error | 5 | Output | tx_core_clkout | Not used. |
The following timing diagram shows an example of TX data transmissions of 10 words from user logic across 10 TX serial lanes.
Name | Width | Direction | Clock Domain | Description |
---|---|---|---|---|
rx_avs_ready | 1 | Input | rx_core_clkout | Avalon® streaming signal. When asserted, indicates that the user logic is ready to accept data. |
rx_avs_data |
64*N | Output | rx_core_clkout | Avalon® streaming signal. RX data. |
rx_avs_channel | 8 | Output | rx_core_clkout | Avalon® streaming signal. The channel number for data being received on the current cycle.This signal is not available in Basic mode. |
rx_avs_valid | 1 | Output | rx_core_clkout | Avalon® streaming signal. When asserted, indicates the RX data signal is valid. |
rx_avs_startofpacket | 1 | Output | rx_core_clkout | Avalon® streaming signal. When asserted, indicates the start of an RX data packet. Assert for only a single clock cycle for each packet. This signal is not available in Basic mode. |
rx_avs_endofpacket | 1 | Output | rx_core_clkout | Avalon® streaming signal. When asserted, indicates the end of an RX data packet. Assert for only a single clock cycle for each packet. This signal is not available in Basic mode. |
rx_avs_empty | 5 | Output | rx_core_clkout | Avalon® streaming signal. Indicates the number of non-valid words in the final burst of the RX data. This signal is not available in Basic mode.
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rx_num_valid_bytes_eob | 4 | Output | rx_core_clkout | Indicates the number of valid bytes in the last word of the final burst. This signal is not available in Basic mode. |
rx_is_usr_cmd | 1 | Output | rx_core_clkout | When asserted, this signal initiate a user-defined information cycle. Assert this signal at the same clock cycle as tx_startofpacket assertion. This signal is not available in Basic mode. |
rx_link_up | 1 | Output | rx_core_clkout | When asserted, indicates the RX data link is ready for data reception. |
rx_link_reinit | 1 | Input | rx_core_clkout | When asserted, this signal initiates lanes re-alignment. If you disable Enable Auto Alignment, assert this signal for one clock cycle to trigger the MAC to re-align the lanes. If the Enable Auto Alignment is set, the MAC re-align the lanes automatically. Do not assert this signal when Enable Auto Alignment is set. |
rx_error | (N*2)+3 | Output | rx_core_clkout | When asserted, indicates error conditions occur in the RX datapath.
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