Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 813669
Date 4/07/2025
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Document Table of Contents
Document Table of Contents x
1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 3 and Agilex™ 5 devices 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Configuration Register Space 6. Interface Signals 7. Design Considerations 8. Timing Constraints 9. Testbench 10. Triple-Speed Ethernet Debug Checklist 11. Software Programming Interface 12. Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 13. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs A. Ethernet Frame Format B. Simulation Parameters
1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 3 and Agilex™ 5 devices x
1.1. Release Information 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Features 1.5. 10/100/1000 Ethernet MAC Versus Small MAC 1.6. High-Level Block Diagrams 1.7. Performance and Resource Utilization
2. Getting Started x
2.1. Introduction to Altera IP Cores 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. IP Core Generation Output 2.5. Simulating Intel® FPGA IP Cores
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel FPGA IP Evaluation Mode
2.4. IP Core Generation Output x
2.4.1. Design Constraint File
3. Parameter Settings x
3.1. Core Configuration 3.2. Ethernet MAC Options 3.3. FIFO Options 3.4. PCS/Transceiver Options 3.5. Analog Parameter Settings
4. Functional Description x
4.1. 10/100/1000 Ethernet MAC 4.2. 1000BASE-X/SGMII PCS With Optional Embedded PMA (GTS) 4.3. HPS GMII Adapter
4.1. 10/100/1000 Ethernet MAC x
4.1.1. MAC Architecture 4.1.2. MAC Interfaces 4.1.3. MAC Transmit Datapath 4.1.4. MAC Receive Datapath 4.1.5. MAC Transmit and Receive Latencies 4.1.6. FIFO Buffer Thresholds 4.1.7. Congestion and Flow Control 4.1.8. Magic Packets 4.1.9. MAC Local Loopback 4.1.10. MAC Reset 4.1.11. PHY Management (MDIO) 4.1.12. Connecting MAC to External PHYs
4.1.3. MAC Transmit Datapath x
4.1.3.1. IP Payload Re-alignment 4.1.3.2. Address Insertion 4.1.3.3. Frame Payload Padding 4.1.3.4. CRC-32 Generation 4.1.3.5. Interpacket Gap Insertion 4.1.3.6. Collision Detection in Half-Duplex Mode
4.1.4. MAC Receive Datapath x
4.1.4.1. Preamble Processing 4.1.4.2. Collision Detection in Half-Duplex Mode 4.1.4.3. Address Checking 4.1.4.4. Frame Type Validation 4.1.4.5. Payload Pad Removal 4.1.4.6. CRC Checking 4.1.4.7. Length Checking 4.1.4.8. Frame Writing 4.1.4.9. IP Payload Alignment
4.1.4.3. Address Checking x
4.1.4.3.1. Unicast Address Checking 4.1.4.3.2. Multicast Address Resolution
4.1.6. FIFO Buffer Thresholds x
4.1.6.1. Receive Thresholds 4.1.6.2. Transmit Thresholds 4.1.6.3. Transmit FIFO Buffer Underflow
4.1.7. Congestion and Flow Control x
4.1.7.1. Remote Device Congestion 4.1.7.2. Receive FIFO Buffer and Local Device Congestion
4.1.8. Magic Packets x
4.1.8.1. Sleep Mode 4.1.8.2. Magic Packet Detection
4.1.11. PHY Management (MDIO) x
4.1.11.1. MDIO Connection 4.1.11.2. MDIO Frame Format
4.1.12. Connecting MAC to External PHYs x
4.1.12.1. Gigabit Ethernet 4.1.12.2. Programmable 10/100 Ethernet 4.1.12.3. Programmable 10/100/1000 Ethernet Operation
4.2. 1000BASE-X/SGMII PCS With Optional Embedded PMA (GTS) x
4.2.1. 1000BASE-X/SGMII PCS Architecture 4.2.2. Transmit Operation 4.2.3. Receive Operation 4.2.4. Transmit and Receive Latencies 4.2.5. GMII Converter 4.2.6. SGMII Converter 4.2.7. Auto-Negotiation 4.2.8. Ten-bit Interface 4.2.9. 1000BASE-X/SGMII PCS Reset
4.2.2. Transmit Operation x
4.2.2.1. Frame Encapsulation 4.2.2.2. 8b/10b Encoding
4.2.3. Receive Operation x
4.2.3.1. Comma Detection 4.2.3.2. 8b/10b Decoding 4.2.3.3. Frame De-encapsulation 4.2.3.4. Synchronization 4.2.3.5. Carrier Sense 4.2.3.6. Collision Detection
4.2.6. SGMII Converter x
4.2.6.1. Transmit 4.2.6.2. Receive
4.2.7. Auto-Negotiation x
4.2.7.1. 1000BASE-X Auto-Negotiation 4.2.7.2. SGMII Auto-Negotiation
5. Configuration Register Space x
5.1. MAC Configuration Register Space 5.2. PCS Configuration Register Space 5.3. Register Initialization
5.1. MAC Configuration Register Space x
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) 5.1.2. Statistics Counters (Dword Offset 0x18 – 0x38) 5.1.3. Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B) 5.1.4. Supplementary Address (Dword Offset 0xC0 – 0xC7)
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) x
5.1.1.1. Command_Config Register (Dword Offset 0x02)
5.2. PCS Configuration Register Space x
5.2.1. Control Register (Word Offset 0x00) 5.2.2. Status Register (Word Offset 0x01) 5.2.3. Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05) 5.2.4. An_Expansion Register (Word Offset 0x06) 5.2.5. If_Mode Register (Word Offset 0x14)
5.2.3. Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05) x
5.2.3.1. 1000BASE-X 5.2.3.2. SGMII MAC Mode Auto Negotiation 5.2.3.3. SGMII PHY Mode Auto Negotiation
5.3. Register Initialization x
5.3.1. Triple-Speed Ethernet System with MII/GMII or RGMII 5.3.2. Triple-Speed Ethernet System with SGMII 5.3.3. Triple-Speed Ethernet System with 1000BASE-X Interface
6. Interface Signals x
6.1. Interface Signals 6.2. Timing
6.1. Interface Signals x
6.1.1. 10/100/1000 Ethernet MAC Signals 6.1.2. 10/100/1000 Multiport Ethernet MAC Signals 6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals 6.1.5. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.6. 1000BASE-X/SGMII PCS Signals 6.1.7. 1000BASE-X/SGMII PCS and PMA (LVDS) Signals 6.1.8. 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.9. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) Signals 6.1.10. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) Signals
6.1.1. 10/100/1000 Ethernet MAC Signals x
6.1.1.1. Clock and Reset Signals 6.1.1.2. Clock Enabler Signals 6.1.1.3. MAC Control Interface Signals 6.1.1.4. MAC Status Signals 6.1.1.5. MAC Receive Interface Signals 6.1.1.6. MAC Transmit Interface Signals 6.1.1.7. Pause and Magic Packet Signals 6.1.1.8. MII/GMII/RGMII Signals 6.1.1.9. PHY Management Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals x
6.1.2.1. Multiport MAC Clock and Reset Signals 6.1.2.2. Multiport MAC Receive Interface Signals 6.1.2.3. Multiport MAC Transmit Interface Signals 6.1.2.4. Multiport MAC Packet Classification Signals 6.1.2.5. Multiport MAC FIFO Status Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals x
6.1.3.1. TBI Interface Signals 6.1.3.2. Status LED Control Signals 6.1.3.3. SERDES Control Signals
6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals x
6.1.4.1. GMII Clock Signals 6.1.4.2. GTS Transceiver Direct PHY Signals 6.1.4.3. GTS Reset Sequencer Signals 6.1.4.4. PMA Reconfiguration Interface Signals
6.1.6. 1000BASE-X/SGMII PCS Signals x
6.1.6.1. PCS Control Interface Signals 6.1.6.2. PCS Reset Signals 6.1.6.3. MII/GMII Clocks and Clock Enablers 6.1.6.4. GMII 6.1.6.5. MII 6.1.6.6. SGMII Status Signals
6.1.8. 1000BASE-X/SGMII 2XTBI PCS Signals x
6.1.8.1. Clock Enablers 6.1.8.2. PCS Reset Signals 6.1.8.3. TBI Interface Signals
6.1.9. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) Signals x
6.1.9.1. 1.25 Gbps LVDS Serial Interface
6.2. Timing x
6.2.1. Avalon Streaming Receive Interface 6.2.2. Avalon Streaming Transmit Interface 6.2.3. GMII Transmit 6.2.4. GMII Receive 6.2.5. RGMII Transmit 6.2.6. RGMII Receive 6.2.7. MII Transmit 6.2.8. MII Receive
7. Design Considerations x
7.1. Exposed Ports in the New User Interface 7.2. Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA (GTS)
8. Timing Constraints x
8.1. Creating Clock Constraints 8.2. Recommended Clock Frequency
9. Testbench x
9.1. Triple-Speed Ethernet Testbench Architecture 9.2. Testbench Components 9.3. Testbench Verification 9.4. Testbench Configuration 9.5. Test Flow 9.6. Simulation Model
9.6. Simulation Model x
9.6.1. Generate the Simulation Model 9.6.2. Simulate the IP 9.6.3. Simulation Model Files
10. Triple-Speed Ethernet Debug Checklist x
10.1. Debug Checklist 10.2. Case Study
10.2. Case Study x
10.2.1. Avalon Streaming Interface 10.2.2. Statistic Counter 10.2.3. Packet Drop 10.2.4. Congestion and Flow Control 10.2.5. Loopback 10.2.6. Link Synchronization
11. Software Programming Interface x
11.1. Driver Architecture 11.2. Directory Structure 11.3. PHY Definition 11.4. Using Multiple SG-DMA Descriptors 11.5. Using Jumbo Frames 11.6. API Functions 11.7. Constants
11.6. API Functions x
11.6.1. alt_tse_mac_get_common_speed() 11.6.2. alt_tse_mac_set_common_speed() 11.6.3. alt_tse_phy_add_profile() 11.6.4. alt_tse_system_add_sys() 11.6.5. tse_mac_setMIImode() 11.6.6. tse_mac_SwReset()
A. Ethernet Frame Format x
A.1. Basic Frame Format A.2. VLAN and Stacked VLAN Frame Format A.3. Pause Frame Format
A.3. Pause Frame Format x
A.3.1. Pause Frame Generation
B. Simulation Parameters x
B.1. Functionality Configuration Parameters B.2. Test Configuration Parameters
1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 3 and Agilex™ 5 devices
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Triple-Speed Ethernet Debug Checklist
11. Software Programming Interface
12. Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
13. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
A. Ethernet Frame Format
B. Simulation Parameters

13. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

Document Version Quartus® Prime Version IP Version Changes
2025.04.07 25.1 8.0.0
  • Added Agilex™ 3 devices information in the Device Speed Grade Support table.
  • Updated Analog Parameter Settings table table:
    • Removed Selects value of RX termination mode parameter.
    • Added rx_eq_vga_gain, rx_eq_hf_boost, rx_eq_dfe_tap_1 parameter.
  • Added o_refclk_bus_out in the GTS Reset Sequencer Signals table.
  • Updated the description for rx_clk signal in the GMII/RGMII/MII Clock Signals table.
  • Updated the following signal name in 1.25 Gbps Interface Signals table:
    • rxp<_n>
    • rxn<_n>
    • txp<_n>
    • txn<_n>
  • Added reference to the Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank in the Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA (GTS) topic.
  • Updated LVDS I/O and GTS transceiver type description in the Core Configuration Parameters table to add list of variations available.
  • Updated 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals diagram to add o_refclk_bus_out signal.
  • Added o_refclk_bus_out in the GTS Reset Sequencer Signals table.
2025.01.23 24.3.1 7.0.0
  • Added Device Speed Grade Support topic.
  • Updated Resource Utilization for Agilex™ 5 Devices table in the Performance and Resource Utilization topic to add two 1000BASE-X/SGMII PCS variants.
  • Updated Core Configuration Parameters in the Core Configuration topic to include Enable HPS GMII Adapter parameter option.
  • Added 1000BASE-X/SGMII PCS with Embedded PMA in the 1000BASE-X/SGMII PCS Architecture topic.
  • Updated PCS Transmit and Receive Latency table to include the following PCS configuration:
    • HPS GMII Adapter with 10 Mbps SGMII PCS and LVDS I/O PMA.
    • HPS GMII Adapter with 100 Mbps SGMII PCS and LVDS I/O PMA.
    • HPS GMII Adapter with 1000 Mbps SGMII PCS and LVDS I/O PMA.
  • Added HPS GMII Adapter topic.
  • Added footnotes for HD_ENA, EXCESS_COL, and LATE_COL field in the Command_Config Register Field Descriptions table.
  • Removed MII in the description for the LOOP_ENA field in the Command_Config Register Field Descriptions table.
  • Updated 1000BASE-X/SGMII PCS Function Signals diagram.
  • Added GMII Signals with HPS GMII Adapter table in the GMII topic.
  • Added the following topic in the Interface Signals:
    • 1000BASE-X/SGMII PCS and PMA (LVDS) Signals topic
  • Added Debug Checklist topic.
  • Added Software Programming Interface topic.
2024.10.07 24.3 6.0.0
  • Added information about LVDS I/O in the following:
    • Added 10/100/1000 Mbps Ethernet MAC and 1000BASE-X/SGMII PCS with LVDS diagram in the High-Level Block Diagrams topic.
    • Updated Features topic.
    • Added resource utilization for 10/100/1000 Mb Ethernet MAC (Fifoless) with 1000BASE-X/SGMII PCS variant in the Resource Utilization for Agilex™ 5 Devices table in the Performance and Resource Utilization topic.
    • Updated Core Configuration Parameters table in the Core Configuration topic.
    • Updated MAC Options Parameters table in the Ethernet MAC Options topic.
    • Updated PCS Transmit and Receive Latency table in the Transmit and Receive Latencies topic to include LVDS I/O latency values.
    • Added 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) Signals topic.
    • Added 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) Signals topic.
    • Updated Recommended Clock Input Frequency For Each IP Variant table in the Recommended Clock Frequency topic to include 10/100/1000 Mbps Multi-channel Ethernet MAC with 1000BASE-X/SGMII PCS (without Internal FIFO buffers) and LVDS I/O Transceiver variant.
  • Updated HW reset value for 0x12 word offset in the PCS Configuration Registers table.
  • Added a note in the SGMII Auto-Negotiation topic.
  • Updated Simulation Model Files table to include aldec directory.
  • Updated the recommended frequency for the REG_CLK signal for the 1000BASE-X/SGMII 2XTBI PCS only variant in the Recommended Clock Input Frequency For Each IP Variant table.
2024.07.08 24.2 5.0.0
  • Added a note about Agilex™ 5 D-Series FPGAs and SoCs support in the About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices topic.
  • Removed /synopsys/vcs from Output Files of Intel® FPGA IP Generation table.
  • Updated PCS/Transceiver Options Parameters topic to include GTS Mono Transceiver Options.
  • Added Analog Parameter Settings topic.
  • Updated 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals figure.
  • Updated GTS Transceiver Direct PHY Signals table.
  • Added PMA Reconfiguration Interface Signals topic.
  • Updated Clock Connectivity for MAC with 2XTBI PCS and Embedded PMA (GTS) figure.
2024.04.01 24.1 4.0.0 Initial release.
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