Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

ID 813663
Date 4/07/2025
Public

Visible to Intel only — GUID: nfa1423215696734

Ixiasoft

Document Table of Contents

6.2. Register Access Definition

Table 34.  Types of Register Access
Access Definition
RO Read only.
RW Read and write.
RWC Read, and write and clear. The user application writes 1 to the register bit(s) to invoke a defined instruction. The IP clears the bit(s) upon executing the instruction.