Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 813663
Date 4/07/2025
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Document Table of Contents
Document Table of Contents x
1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview 2. Getting Started 3. Functional Description 4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 5. Interface Signals 6. Configuration Registers 7. Debug Checklist 8. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 9. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview x
1.1. Features 1.2. Release Information 1.3. Low Latency Ethernet 10G MAC Operating Modes 1.4. Device Family Support 1.5. Performance and Resource Utilization
1.5. Performance and Resource Utilization x
1.5.1. Resource Utilization 1.5.2. TX and RX Latency
2. Getting Started x
2.1. Introduction to Altera IP Cores 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IP Cores 2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core x
2.6.1. Design Considerations
2.6.1. Design Considerations x
2.6.1.1. Timing Constraints
2.6.1.1. Timing Constraints x
2.6.1.1.1. Pseudo-Static CSR Fields 2.6.1.1.2. Clock Crosser 2.6.1.1.3. Dual Clock FIFO
2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples x
2.7.1. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example for Agilex™ 3 and Agilex™ 5 Devices
3. Functional Description x
3.1. Architecture 3.2. Interfaces 3.3. Frame Types 3.4. TX Datapath 3.5. RX Datapath 3.6. Flow Control 3.7. Reset Requirements 3.8. XGMII Error Handling (Link Fault) 3.9. IEEE 1588v2
3.4. TX Datapath x
3.4.1. Padding Bytes Insertion 3.4.2. Address Insertion 3.4.3. CRC-32 Insertion 3.4.4. XGMII Encapsulation 3.4.5. Inter-Packet Gap Generation and Insertion 3.4.6. XGMII Transmission 3.4.7. TX Promiscuous (Transparent) Mode 3.4.8. TX Timing Diagrams
3.5. RX Datapath x
3.5.1. XGMII Decapsulation 3.5.2. CRC Checking 3.5.3. Address Checking 3.5.4. Frame Type Checking 3.5.5. Length Checking 3.5.6. CRC and Padding Bytes Removal 3.5.7. Overflow Handling 3.5.8. RX Promiscuous (Transparent) Mode 3.5.9. RX Timing Diagrams
3.5.5. Length Checking x
3.5.5.1. Frame Length 3.5.5.2. Payload Length
3.6. Flow Control x
3.6.1. IEEE 802.3 Flow Control 3.6.2. Priority-Based Flow Control
3.6.1. IEEE 802.3 Flow Control x
3.6.1.1. Pause Frame Reception 3.6.1.2. Pause Frame Transmission
3.6.2. Priority-Based Flow Control x
3.6.2.1. PFC Frame Reception 3.6.2.2. PFC Frame Transmission
3.9. IEEE 1588v2 x
3.9.1. Architecture 3.9.2. TX Datapath 3.9.3. RX Datapath 3.9.4. Frame Format
3.9.4. Frame Format x
3.9.4.1. PTP Packet in IEEE 802.3 3.9.4.2. PTP Packet over UDP/IPv4 3.9.4.3. PTP Packet over UDP/IPv6
5. Interface Signals x
5.1. Clock and Reset Signals 5.2. Speed Selection Signal 5.3. Error Correction Signals 5.4. Avalon® Memory-Mapped Interface Programming Signals 5.5. Avalon® Streaming Data Interfaces 5.6. Avalon® Streaming Flow Control Signals 5.7. Avalon® Streaming Status Interface 5.8. PHY-side Interfaces 5.9. IEEE 1588v2 Interfaces
5.5. Avalon® Streaming Data Interfaces x
5.5.1. Avalon® Streaming TX Data Interface Signals 5.5.2. Avalon® Streaming RX Data Interface Signals 5.5.3. Avalon® Streaming Data Interface Clocks
5.7. Avalon® Streaming Status Interface x
5.7.1. Avalon® Streaming Interface TX Status Signals 5.7.2. Avalon® Streaming Interface RX Status Signals
5.8. PHY-side Interfaces x
5.8.1. XGMII TX Signals 5.8.2. XGMII RX Signals 5.8.3. GMII TX Signals 5.8.4. GMII RX Signals 5.8.5. MII TX Signals 5.8.6. MII RX Signals
5.9. IEEE 1588v2 Interfaces x
5.9.1. IEEE 1588v2 Egress TX Signals 5.9.2. IEEE 1588v2 Ingress RX Signals 5.9.3. IEEE 1588v2 Interface Clocks
6. Configuration Registers x
6.1. Register Map 6.2. Register Access Definition 6.3. Primary MAC Address 6.4. MAC Reset Control Register 6.5. TX Configuration and Status Registers 6.6. Flow Control Registers 6.7. RX Configuration and Status Registers 6.8. ECC Registers 6.9. Statistics Registers 6.10. Timestamp Registers
6.10. Timestamp Registers x
6.10.1. Calculating PHY Total Latency 6.10.2. Calculating Deterministic Latency 6.10.3. PTP Register Configuration
7. Debug Checklist x
7.1. Pre-Debugging Process 7.2. Clock Frequency 7.3. Recommended Reset Handling 7.4. Recommended Signals for Signal Tap
1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
2. Getting Started
3. Functional Description
4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
5. Interface Signals
6. Configuration Registers
7. Debug Checklist
8. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
9. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

9. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

Document Version Quartus® Prime Version IP Version Changes
2025.04.07 25.1 5.0.0
  • Updated Speed Mode Comparison of the Low Latency Ethernet 10G MAC Intel® FPGA IP table to update 1G/2.5G/5G/10G Multirate Ethernet PHY in the Intel PHY Compliance column.
  • Updated Device Family Support table to include information about Agilex™ 3 devices.
  • Updated the Signals for Signal Tap topic title to Recommended Signals for Signal Tap.
2025.01.23 24.3.1 4.0.0
  • Updated MAC features information and PHY-side interfaces information in the Features topic.
  • Updated Speed Mode Comparison of the LL Ethernet 10G MAC Intel FPGA IP Core table to include 10G, 1G/10G, 10M/100M/1G/10G, and 1G/2.5G/10G speed mode.
  • Updated Resource Utilization for LL Ethernet 10G MAC for Agilex™ 5 Devices to include 10G, 1G/10G, 1G/2.5G/10G, and 10M/100M/1G/10G operating mode.
  • Updated TX and RX Latency Values for Agilex 5 Devices table to include 10G, 1G/10G, 1G/2.5G/10G, and 10M/100M/1G/10G MAC operating modes.
  • Updated Upgrading IP Components in Project Navigator figure.
  • Updated Low Latency Ethernet 10G MAC Block Diagram.
  • Updated the Interfaces table:
    • Added the description about 1G/10G and 10M/100M/1G/10G operating modes for GMII.
    • Added information about MII interface.
  • Updated the Low Latency Ethernet 10G MAC Intel® FPGA IP Core Parameters table:
    • Updated the value column for Speed parameter to add 10G, 1G/10G, 10M/100M/1G/10G, and 1G/2.5G/10G options.
    • Updated value column for Datapath options parameter to add TX only and RX only options.
  • Updated Speed Selection Signal table to include 10G, 1G/10G,10M/100M/1G/10G operating mode.
  • Updated GMII TX Signals table to include the following signals:
    • gmii_tx_clk
    • gmii_tx_d[]
    • gmii_tx_en
    • gmii_tx_err
  • Updated GMII RX Signals table to include the following signals:
    • gmii_rx_clk
    • gmii_rx_d[]
    • gmii_rx_dv
    • gmii_rx_err
  • Added MII TX Signals topic.
  • Added MII RX Signals topic.
  • Added Debug Checklist topic.
2024.10.07 24.3 3.0.0
  • Updated the note in the Low Latency Ethernet 10G MAC Intel® FPGA IP Overview topic.
  • Removed the note about Agilex™ 5 D-Series FPGAs and SoCs device support in the Low Latency Ethernet 10G MAC Intel® FPGA IP Overview topic.
  • Updated MAC features in the Features topic.
  • Updated Speed Mode Comparison of the LL Ethernet 10G MAC Intel FPGA IP Core table to include 10M/100M/1G/2.5G/10G speed mode.
  • Updated Generated IP Files table to include aldec.
  • Updated Low Latency Ethernet 10G MAC Block Diagram.
  • Added information about 10M/100M/1G/2.5G/10G operating mode:
    • Updated Device Family Support table.
    • Updated Resource Utilization for LL Ethernet 10G MAC for Agilex™ 5 Devices table.
    • Updated TX and RX Latency Values for Agilex™ 5 Devices table.
    • Updated Interfaces table.
    • Updated Interface Signals figure.
    • Updated Low Latency Ethernet 10G MAC Intel FPGA IP Core Parameters table.
    • Updated Clock and Reset Signals table.
    • Updated Speed Selection Signal table.
    • Updated XGMII Transmit Signals table to add xgmii_tx[] signal.
    • Updated XGMII Receive Signals table to add xgmii_rx[] signal.
    • Updated GMII TX Signals table.
    • Updated GMII RX Signals table.
    • Updated Clock Enable Signals table.
  • Removed tx_path_delay_10g_data[15:0] signal in the IEEE 1588v2 Egress TX Signals table.
  • Removed rx_path_delay_10g_data[15:0] signal in the IEEE 1588v2 Ingress RX Signals table.
  • Removed 10M/100M/1G/2.5G speed from Clock Signals for the IEEE 1588V2 Interfaces table.
  • Removed 2.5G (MGBASE) from 0.8ns in the value for the UI period in the Deterministic Latency Parameter Description table.
2024.07.08 24.2 2.1.0
  • Added a note about Agilex™ 5 D-Series FPGAs and SoCs support in the Low Latency Ethernet 10G MAC Intel FPGA IP Overview topic.
  • Updated Device Family Support table.
  • Removed synopsys/vcs/ file name from Generated IP Files table.
  • Updated XON Pause Frame Transmission figure.
  • Updated description for csr_clk signal in the Clock and Reset Signals table.
  • Updated Timestamp Registers table.
  • Updated Calculating PHY Total Latency topic.
  • Updated Calculating Deterministic Latency topic.
  • Updated PTP Register Configuration topic.
2024.04.01 24.1 2.0.0 Initial public release.
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