Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813654
Date 1/23/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Testing the Design Example in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
1.3. Simulating the Design Example x
1.3.1. Simulation Design Example Components
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Compile the Design Example in Hardware 1.4.2. Configure the Clocks in Hardware 1.4.3. Program the FPGA
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Design Example Registers 2.5. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Design Example Registers x
2.4.1. Hardware Design Example Register Map 2.4.2. Packet Client Registers
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

1.5. Testing the Design Example in Hardware

After compiling the Low Latency 40G Ethernet  Intel® FPGA IP core design example and configuring it on your  Agilex™ 5 device, you can use the System Console to program the IP core and its embedded Native PHY IP core registers.
To turn on the System Console and test the hardware design example, follow these steps:
  1. Navigate to the <design_example>/hardware_test_design directory.
  2. In the Quartus® Prime Pro Edition software, select Tools > System Debugging Tools > System Console or type system-console & to launch the system console.
  3. In the Tcl Console panel, type cd hwtest to change the working directory to <design_example_dir >/hardware_test_design/hwtest.
  4. Type source main.tcl to open a connection to the JTAG master and start the test.
  5. Run the following commands in the System Console Tcl shell. 
    source main.tcl
set_jtag <number_of_appropriate_JTAG_master>
  6. Run one of the following commands:
    • If you use the internal serial loopback, enter
      run_test_silb
    The hardware design example commands are available to program the IP core:
    • chkphy_status: Displays the clock frequencies and PHY lock status.
    • chkmac_stats: Displays the values in the MAC statistics counters.
    • clear_all_stats: Clears the IP core statistics counters.
    • start_pkt_gen: Starts the packet generator.
    • stop_pkt_gen: Stops the packet generator
    • loop_on: Turns on internal serial loopback.
    • loop_off: Turns off internal serial loopback.
    • reg_read <addr>: Returns the IP core register value at <addr>.
    • reg_write <addr> <data>: Writes <data> to the IP core register at the address <addr>.
    • If you inserted an external QSFP28 loopback module in to QSFP1(J12) port, enter: 
      run_test_elb
    The hardware design example uses this command to initiate packet transmission from the packet generator to the Intel® FPGA IP core. Specifically, the script performs the following steps:
    • chkphy_status: Displays the clock frequencies and PMA PHY lock status.
    • chkmac_stats: Displays the MAC statistics counters.
    • clear_all_stats: Clears the IP core statistics counters.
    • start_pkt_gen: Starts the packet generator.
    • stop_pkt_gen: Stops the packet generator.
The following sample output illustrates a successful hardware test run:
Figure 8. Sample OutputClock frequency of i_reconfig_clk/csr_clk  is 100 MHz.
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