Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813654
Date 1/23/2025
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Testing the Design Example in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
1.3. Simulating the Design Example x
1.3.1. Simulation Design Example Components
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Compile the Design Example in Hardware 1.4.2. Configure the Clocks in Hardware 1.4.3. Program the FPGA
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Design Example Registers 2.5. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Design Example Registers x
2.4.1. Hardware Design Example Register Map 2.4.2. Packet Client Registers
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

1.4.1. Compile the Design Example in Hardware

To compile the hardware design example and configure it on your Agilex™ 5 device, follow these steps:
  1. Ensure that the hardware design example generation is complete.
  2. In the Quartus® Prime Pro Edition software, navigate to the Quartus® Prime project directory at <design_example_dir>/hardware_test_design/eth_ex_40g.qpf.
  3. Click Processing > Start Compilation.
  4. Verify that the IP generates the bitstream file (.sof) and meets the timing requirements.
  5. After a successful compilation, a .sof is available in <design_example_directory>/hardwarde_test_design/output_files directory.
    Figure 5. Compilation Flow
Level Two Title