Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 813266
Date 6/12/2024
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Document Table of Contents
Document Table of Contents x
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs x
1.1. Pins Status for Agilex™ 5 Devices 1.2. Agilex™ 5 FPGA Core Pins 1.3. Agilex™ 5 GTS Transceiver Pins 1.4. Agilex™ 5 Hard Processor System (HPS) Pins 1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices 1.6. Notes to Agilex™ 5 Pin Connection Guidelines 1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1.2. Agilex™ 5 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. HVIO GPIO Pins 1.2.10. HVIO Optional Function Pins 1.2.11. No Connect and DNU Pins 1.2.12. Power Supply Pins 1.2.13. Secure Device Manager (SDM) Pins 1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 5 GTS Transceiver Pins x
1.3.1. GTS Transceiver Power Supply Pins 1.3.2. GTS Transceiver Pins
1.4. Agilex™ 5 Hard Processor System (HPS) Pins x
1.4.1. HPS Power Supply Pins 1.4.2. HPS Oscillator Clock Input Pin 1.4.3. HPS JTAG Pins 1.4.4. HPS GPIO Pins 1.4.5. HPS SDMMC Pins 1.4.6. HPS NAND Pins 1.4.7. HPS USB Pins 1.4.8. HPS EMAC Pins 1.4.9. HPS I2C_EMAC and MDIO Pins 1.4.10. HPS I2C Pins 1.4.11. HPS I3C Pins 1.4.12. HPS SPI Pins 1.4.13. HPS UART Pins 1.4.14. HPS Trace Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices x
1.5.1. Example 1— Agilex™ 5 Devices with Speed Grade -1V, -2V, -2E, and -3V 1.5.2. Example 2— Agilex™ 5 Devices with Speed Grade -4S, -5S, -6S, and -6X
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

1.5.2. Example 2— Agilex™ 5 Devices with Speed Grade -4S, -5S, -6S, and -6X

Table 33.  Power Supply Sharing Guidelines for Agilex™ 5 Devices with Speed Grade 4S, -5S, -6S, and -6XExample Requiring 5 Power Regulators
Power Pin Name Regulator Group Voltage Level (V) Supply Tolerance Power Source Regulator Sharing Notes
VCC 1

0.8 (-4S)

0.78 (-5S)

0.75 (-6S, -6X)

 ±3% Switcher 4 Share Connect VCC and VCCP to a dedicated 0.8-V, 0.78-V, or 0.75-V power supply. For the power supply voltage level, refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet .
VCCP Speed Grade Voltage (V)
VCCL_HPS -4S 0.8
VCCL_HPS_CORE0_CORE1 -5S 0.78
VCCL_HPS_CORE2 -6S 0.75
VCCL_HPS_CORE3 -6X 0.75
VCCPLLDIG1_HPS Filter

You have the option to connect VCCL_HPS, VCCL_SDM, VCC_HSSI, VCC_IO_SDM, and VCCL_ADC_SDM to the same regulator as VCC and VCCP when the power rails require the same voltage level. You may also connect the VCCPLLDIG1_HPS, VCCPLLDIG2_HPS, and VCCPLLDIG_SDM to the shared VCC, VCCP, and VCCL_HPS power planes with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Agilex™ 5 device, you must still provide power to these power supply pins. Do not leave the VCCL_HPS and VCCPLLDIG_HPS power supply pins floating or connected to GND.

VCCPLLDIG2_HPS
VCCL_SDM Share
VCC_HSSI
VCC_IO_SDM
VCCL_ADC_SDM
VCCPLLDIG_SDM Filter
VCCERT_GTS 2 1.0 ±2.5% Switcher4 and Linear Share

Connect to a dedicated 1.0-V power supply.

For non-transceiver device, VCCH_SDM can be 0.8 V, 0.78 V, or 0.75 V depending on the speed grade. You have the option to merge VCCH_SDM with VCCL_SDM.

VCCH_SDM
VCCPT 3 1.8 ±2.5% Switcher4 Share

Connect VCCPT to a dedicated 1.8-V power supply.

Connect VCCADC, VCCPLL_SDM, VCCPLL1_HPS, VCCPLL2_HPS, and VCCEHT_GTS to the same power plane with proper isolation filtering.

Depending on the regulator capabilities, you have the option to share this supply with multiple Agilex™ 5 devices.

VCCPT_HVIO
VCCIO_SDM
VCCIO_HPS
VCCFUSEWR_SDM
VCCPLL1_HPS Filter
VCCPLL2_HPS
VCCADC Filter
VCCPLL_SDM
VCCEHT_GTS Filter
VCCRCORE 4 1.2 ±5% or ±3% 5 Switcher4 Share Connect to a dedicated 1.2-V power supply. If you have LVDS Tx signals on the sub-bank of your board, the VCCIO_PIO of this sub-bank is 1.3 V. In this case, you require another VR to support this sub-bank.
VCCIO_PIO_T/B
VCCIO_PIO_SDM
VCCIO_HVIO 5 3.3/2.5/1.8 ±3% Switcher4 Isolate Connect to a dedicated 3.3-V, 2.5-V, 1.8-V power supply.

Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Agilex™ 5 devices is provided in the following figure.

Figure 2. Example Power Supply Sharing Guidelines for Agilex™ 5 Devices with Speed Grade -4S, -5S, -6S, and -6X
Related Information
4 When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 4 of the Notes to Agilex™ 5 Pin Connection Guidelines .
5 Refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet for VCCIO_PIO use cases, to decide the voltage tolerance is ± 3% or ± 5%.
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