Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 813266
Date 8/11/2025
Public
Document Table of Contents
Document Table of Contents x
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs x
1.1. Pin Connection Guideline Status for Agilex™ 5 Devices 1.2. Agilex™ 5 FPGA Core Pins 1.3. Agilex™ 5 GTS Transceiver Pins 1.4. Agilex™ 5 Hard Processor System (HPS) Pins 1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices 1.6. Notes to Agilex™ 5 Pin Connection Guidelines 1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1.2. Agilex™ 5 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. HVIO GPIO Pins 1.2.10. HVIO Optional Function Pins 1.2.11. No Connect and DNU Pins 1.2.12. Power Supply Pins 1.2.13. Secure Device Manager (SDM) Pins 1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 5 GTS Transceiver Pins x
1.3.1. GTS Transceiver Power Supply Pins 1.3.2. GTS Transceiver Pins
1.4. Agilex™ 5 Hard Processor System (HPS) Pins x
1.4.1. HPS Power Supply Pins 1.4.2. HPS Oscillator Clock Input Pin 1.4.3. HPS JTAG Pins 1.4.4. HPS GPIO Pins 1.4.5. HPS SDMMC Pins 1.4.6. HPS NAND Pins 1.4.7. HPS USB Pins 1.4.8. HPS EMAC Pins 1.4.9. HPS I2C_EMAC and MDIO Pins 1.4.10. HPS I2C Pins 1.4.11. HPS I3C Pins 1.4.12. HPS SPI Pins 1.4.13. HPS UART Pins 1.4.14. HPS Trace Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices x
1.5.1. Example 1— Agilex™ 5 Devices with Speed and Power Grade -1V, -2V, -2E, and -3V 1.5.2. Example 2— Agilex™ 5 Devices with Speed and Power Grade -4S, -5S, -6S, and -6X
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

1.2.4. Differential I/O Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 5.  Differential I/O Pins
Pin Name Pin Functions Pin Description Connection Guidelines

DIFF_IO_[2][A,B]_[T,B][1:24][p,n]

DIFF_IO_[3][A,B]_[T,B][1:24][p,n]

 I/O, RX/TX channel

These are LVDS SERDES channels on HSIO banks. If these pins are not used in LVDS SERDES implementation, these pins are available as user I/O pins.

Supported I/O standards:

  • 1.3-V I/O standard for true differential I/O
  • 1.3-V I/O standard for single-ended non-voltage referenced I/O
  • 1.2-V I/O standard for single-ended voltage referenced and non-voltage referenced I/O
  • 1.2-V I/O standard for differential voltage referenced I/O
  • 1.2-V I/O standard for true differential I/O
  • 1.1-V I/O standard for single-ended voltage referenced and non-voltage referenced I/O
  • 1.1-V I/O standard for differential voltage referenced I/O
  • 1.1-V I/O standard for true differential I/O
  • 1.05-V I/O standard for single-ended voltage referenced and non-voltage referenced I/O
  • 1.05-V I/O standard for differential voltage referenced input
  • 1.05-V I/O standard for true differential I/O
  • 1.0-V I/O standard for non-voltage referenced I/O

These pins support the programmable pull-up resistor. For more information, refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet .

For more information about the I/O placement guidelines, refer to the General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs .

Connect unused pins as defined in the Quartus® Prime software.

If the entire HSIO bank is unused, you may leave these pins floating, connected to VCCIO_PIO, or connected to a tri-stated upstream or downstream I/O pin. If the unused pins reside in an active HSIO bank, you may leave these pins floating or connected to a tri-stated upstream or downstream I/O pin.
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