Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813266
Date 8/11/2025
Public
Document Table of Contents
Document Table of Contents x
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs x
1.1. Pin Connection Guideline Status for Agilex™ 5 Devices 1.2. Agilex™ 5 FPGA Core Pins 1.3. Agilex™ 5 GTS Transceiver Pins 1.4. Agilex™ 5 Hard Processor System (HPS) Pins 1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices 1.6. Notes to Agilex™ 5 Pin Connection Guidelines 1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1.2. Agilex™ 5 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. HVIO GPIO Pins 1.2.10. HVIO Optional Function Pins 1.2.11. No Connect and DNU Pins 1.2.12. Power Supply Pins 1.2.13. Secure Device Manager (SDM) Pins 1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 5 GTS Transceiver Pins x
1.3.1. GTS Transceiver Power Supply Pins 1.3.2. GTS Transceiver Pins
1.4. Agilex™ 5 Hard Processor System (HPS) Pins x
1.4.1. HPS Power Supply Pins 1.4.2. HPS Oscillator Clock Input Pin 1.4.3. HPS JTAG Pins 1.4.4. HPS GPIO Pins 1.4.5. HPS SDMMC Pins 1.4.6. HPS NAND Pins 1.4.7. HPS USB Pins 1.4.8. HPS EMAC Pins 1.4.9. HPS I2C_EMAC and MDIO Pins 1.4.10. HPS I2C Pins 1.4.11. HPS I3C Pins 1.4.12. HPS SPI Pins 1.4.13. HPS UART Pins 1.4.14. HPS Trace Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices x
1.5.1. Example 1— Agilex™ 5 Devices with Speed and Power Grade -1V, -2V, -2E, and -3V 1.5.2. Example 2— Agilex™ 5 Devices with Speed and Power Grade -4S, -5S, -6S, and -6X
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

Document Version Changes
2025.08.11
  • Updated Pins Status for Agilex™ 5 Devices:
    • Retitled topic to Pin Connection Guideline Status for Agilex™ 5 Devices.
    • Added a note about the Agilex™ 5 pin connection statuses.
  • Updated and retitled topic Example 1— Agilex™ 5 Devices with Speed Grade -4S, -5S, -6S, and -6X to Example 1— Agilex™ 5 Devices with Speed and Power Grade -4S, -5S, -6S, and -6X for clarity.
  • Updated and retitled topic Example 2— Agilex™ 5 Devices with Speed Grade -4S, -5S, -6S, and -6X to Example 2— Agilex™ 5 Devices with Speed and Power Grade -4S, -5S, -6S, and -6X for clarity.
  • Updated connection guidelines for VCCL_HPS in Table: HPS Power Supply Pins to state that you must share VCCL_HPS with VCC together.
  • Updated the notes for regulator group 1 in Table: Example 1— Agilex™ 5 Devices with Speed Grade -4S, -5S, -6S, and -6X.
  • Updated the notes for regulator group 1 in Table: Example 2— Agilex™ 5 Devices with Speed Grade -4S, -5S, -6S, and -6X.
2025.05.23
  • Updated the connection guidelines for VCCLSENSE and GNDSENSE for Agilex™ 5 devices of -S and -X speed grades.
  • Updated the connection guidelines for unused HSIO banks and unused pins in an active HSIO bank in the following tables:
    • Table: Clock and PLL Pins
    • Table: Differential I/O Pins
    • Table: External Memory Interface Pins
  • Updated the connection guidelines for VCCEHT_GTS[L1,R4][A,B,C,D] and VCCERT_GTS[L1,R4][A,B,C,D].
  • Removed the notes for I3C0_SDA_PULLUP_EN and I3C1_SDA_PULLUP_EN in Table: HPS I3C Pins.
2024.12.21
  • Updated the connection guidelines for the VREFP_ADC.
  • Made minor editorial edits to the document.
2024.10.17
  • Updated Table: Differential I/O Pins:
    • Updated pin name DIFF_IO_[2][A,B][T,B][1:24][p,n] to DIFF_IO_[2][A,B]_[T,B][1:24][p,n].
    • Updated pin name DIFF_IO_[3][A,B][T,B][1:24][p,n] to DIFF_IO_[3][A,B]_[T,B][1:24][p,n].
  • Updated the VCCIO_PIO connection guidelines for unused HSIO bank and sub-bank in Table: Power Supply Pins.
  • Added new HPS I3C pins in Table: HPS I3C:
    • I3C0_SDA_PULLUP_EN
    • I3C1_SDA_PULLUP_EN
  • Updated the connection guidelines for the AS_nCSO3 pin function of SDM_IO8.
  • Made editorial edits to the connection guidelines of TCK and OSC_CLK_1 in Table: Dedicated Configuration/JTAG Pins for clarity.
2024.07.08 Updated the pin description and connection guidelines for PIN_PERST_N_CVP_L1[A,B,C,D]_[0,1] and PIN_PERST_N_R4[A,B,C,D]_[0,1].
2024.06.12 Updated the connection guidelines for the HPS_COLD_nRESET pin.
2024.04.02 Updated the connection guidelines for the following pins:
  • HPS_COLD_nRESET
  • HPS_OSC_CLK
  • JTAG_TCK
  • JTAG_TMS
  • JTAG_TDO
  • JTAG_TDI
  • GPIO0_IO[0..23]
  • GPIO1_IO[0..23]
2024.04.01 Initial release.
Level Two Title