Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 813266
Date 8/11/2025
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Document Table of Contents
Document Table of Contents x
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs x
1.1. Pin Connection Guideline Status for Agilex™ 5 Devices 1.2. Agilex™ 5 FPGA Core Pins 1.3. Agilex™ 5 GTS Transceiver Pins 1.4. Agilex™ 5 Hard Processor System (HPS) Pins 1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices 1.6. Notes to Agilex™ 5 Pin Connection Guidelines 1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1.2. Agilex™ 5 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. HVIO GPIO Pins 1.2.10. HVIO Optional Function Pins 1.2.11. No Connect and DNU Pins 1.2.12. Power Supply Pins 1.2.13. Secure Device Manager (SDM) Pins 1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 5 GTS Transceiver Pins x
1.3.1. GTS Transceiver Power Supply Pins 1.3.2. GTS Transceiver Pins
1.4. Agilex™ 5 Hard Processor System (HPS) Pins x
1.4.1. HPS Power Supply Pins 1.4.2. HPS Oscillator Clock Input Pin 1.4.3. HPS JTAG Pins 1.4.4. HPS GPIO Pins 1.4.5. HPS SDMMC Pins 1.4.6. HPS NAND Pins 1.4.7. HPS USB Pins 1.4.8. HPS EMAC Pins 1.4.9. HPS I2C_EMAC and MDIO Pins 1.4.10. HPS I2C Pins 1.4.11. HPS I3C Pins 1.4.12. HPS SPI Pins 1.4.13. HPS UART Pins 1.4.14. HPS Trace Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices x
1.5.1. Example 1— Agilex™ 5 Devices with Speed and Power Grade -1V, -2V, -2E, and -3V 1.5.2. Example 2— Agilex™ 5 Devices with Speed and Power Grade -4S, -5S, -6S, and -6X
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

1.4.8. HPS EMAC Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 25.  HPS EMAC PinsThere are three EMAC controllers (EMAC0, EMAC1, and EMAC2) for the Agilex™ 5 HPS.
HPS Pin Function Pin Description and Connection Guidelines Pin Type Valid Assignments
EMAC0_TX_CLK EMAC0 Transmit Clock. Output HPS_IOA_13
EMAC0_TX_CTL EMAC0 Transmit Control. Output HPS_IOA_14
EMAC0_RX_CLK EMAC0 Receive Clock. Input HPS_IOA_15
EMAC0_RX_CTL EMAC0 Receive Control. Input HPS_IOA_16
EMAC0_TXD0 EMAC0 Transmit Data Bit 0. Output HPS_IOA_17
EMAC0_TXD1 EMAC0 Transmit Data Bit 1. Output HPS_IOA_18
EMAC0_RXD0 EMAC0 Receive Data Bit 0. Input HPS_IOA_19
EMAC0_RXD1 EMAC0 Receive Data Bit 1. Input HPS_IOA_20
EMAC0_TXD2 EMAC0 Transmit Data Bit 2. Output HPS_IOA_21
EMAC0_TXD3 EMAC0 Transmit Data Bit 3. Output HPS_IOA_22
EMAC0_RXD2 EMAC0 Receive Data Bit 2. Input HPS_IOA_23
EMAC0_RXD3 EMAC0 Receive Data Bit 3 Input HPS_IOA_24
EMAC0_PPS0 EMAC0 1PPS signal. Output

HPS_IOA_1

HPS_IOB_1
EMAC0_PPSTRIG0 EMAC0 1PPS trigger signal. Input

HPS_IOA_2

HPS_IOB_2
EMAC1_TX_CLK EMAC1 Transmit Clock. Output HPS_IOB_1
EMAC1_TX_CTL EMAC1 Transmit Control. Output HPS_IOB_2
EMAC1_RX_CLK EMAC1 Receive Clock. Input HPS_IOB_3
EMAC1_RX_CTL EMAC1 Receive Control. Input HPS_IOB_4
EMAC1_TXD0 EMAC1 Transmit Data Bit 0. Output HPS_IOB_5
EMAC1_TXD1 EMAC1 Transmit Data Bit 1. Output HPS_IOB_6
EMAC1_RXD0 EMAC1 Receive Data Bit 0. Input HPS_IOB_7
EMAC1_RXD1 EMAC1 Receive Data Bit 1. Input HPS_IOB_8
EMAC1_TXD2 EMAC1 Transmit Data Bit 2. Output HPS_IOB_9
EMAC1_TXD3 EMAC1 Transmit Data Bit 3. Output HPS_IOB_10
EMAC1_RXD2 EMAC1 Receive Data Bit 2. Input HPS_IOB_11
EMAC1_RXD3 EMAC1 Receive Data Bit 3. Input HPS_IOB_12
EMAC1_PPS1 EMAC1 1PPS signal. Output HPS_IOA_3
EMAC1_PPSTRIG1 EMAC1 1PPS trigger signal. Input HPS_IOA_4
EMAC2_TX_CLK EMAC2 Transmit Clock. Output HPS_IOB_13
EMAC2_TX_CTL EMAC2 Transmit Control. Output HPS_IOB_14
EMAC2_RX_CLK EMAC2 Receive Clock. Input HPS_IOB_15
EMAC2_RX_CTL EMAC2 Receive Control. Input HPS_IOB_16
EMAC2_TXD0 EMAC2 Transmit Data Bit 0. Output HPS_IOB_17
EMAC2_TXD1 EMAC2 Transmit Data Bit 1. Output HPS_IOB_18
EMAC2_RXD0 EMAC2 Receive Data Bit 0. Input HPS_IOB_19
EMAC2_RXD1 EMAC2 Receive Data Bit 1. Input HPS_IOB_20
EMAC2_TXD2 EMAC2 Transmit Data Bit 2. Output HPS_IOB_21
EMAC2_TXD3 EMAC2 Transmit Data Bit 3. Output HPS_IOB_22
EMAC2_RXD2 EMAC2 Receive Data Bit 2. Input HPS_IOB_23
EMAC2_RXD3 EMAC2 Receive Data Bit 3. Input HPS_IOB_24
EMAC2_PPS2 EMAC2 1PPS signal. Output

HPS_IOA_5

HPS_IOB_5
EMAC2_PPSTRIG2 EMAC2 1PPS trigger signal. Input

HPS_IOA_6

HPS_IOB_6
Level Two Title