MAX® 10 FPGA 10M08S Evaluation Kit User Guide

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ID 812857
Date 12/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Components 4. Document Revision History for the MAX® 10 FPGA 10M08S Evaluation Kit User Guide A. Safety and Regulatory Compliance Information
1. Overview x
1.1. Board Component Blocks 1.2. Supported Items Not Included with the Kit
2. Getting Started x
2.1. Powering the Kit 2.2. Installing the Intel® FPGA Download Cable Driver 2.3. Handling the Kit 2.4. Factory Default Switch and Jumper Settings
2.3. Handling the Kit x
2.3.1. Handling the DIP Switches
3. Board Components x
3.1. Board Overview 3.2. Featured Device: MAX® 10 FPGA 3.3. Configuration 3.4. Clock Circuitry 3.5. Arduino Connectors 3.6. General User Input/Output 3.7. Power Supply
3.3. Configuration x
3.3.1. FPGA Programming over External Intel® FPGA Download Cable 3.3.2. Configuring the FPGA Using the Quartus® Prime Programmer 3.3.3. Selecting Internal Configuration Scheme 3.3.4. Generating a .pof File with ICB Settings 3.3.5. Programming Internal Flash Memory
3.4. Clock Circuitry x
3.4.1. General-Purpose Clock
3.6. General User Input/Output x
3.6.1. User-Defined DIP Switch 3.6.2. User-Defined LEDs
3.7. Power Supply x
3.7.1. Power Measurement 3.7.2. Power Distribution System 3.7.3. Temperature Sense
A. Safety and Regulatory Compliance Information x
A.1. Safety and Regulatory Information A.2. Compliance Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Board Components
4. Document Revision History for the MAX® 10 FPGA 10M08S Evaluation Kit User Guide
A. Safety and Regulatory Compliance Information

3.3. Configuration

The MAX® 10 FPGA 10M08S Evaluation Kit supports two configuration methods:

  • JTAG header (J10) for configuration by downloading a .sof file to the FPGA. Any power cycling of the FPGA or reconfiguration can power up the FPGA to a blank state.
  • JTAG header (J10) for programming of the on-die FPGA Configuration Flash Memory (CFM) via a .pof file. Any power cycling of the FPGA or reconfiguration can power up the FPGA in self-configuration mode, using the files stored in the CFM.

The Quartus® Prime Convert Programming File (CPF) GUI can be used to generate a .pof file that can use for internal configuration. You can directly program the MAX® 10 device's flash which included Configuration Flash Memory (CFM) and User Flash Memory (UFM) by using a download cable with the Quartus® Prime software programmer.


Section Content
FPGA Programming over External Intel FPGA Download Cable
Configuring the FPGA Using the Quartus Prime Programmer
Selecting Internal Configuration Scheme
Generating a .pof File with ICB Settings
Programming Internal Flash Memory

Level Two Title