Intel® Simics® Simulator for Altera® FPGAs: Agilex™ 5 and Agilex™ 3 Virtual Platform User Guide

ID 786901
Date 9/29/2025
Public
Document Table of Contents

2.1.2. Agilex™ 3 Universal Virtual Platform Overview

The Agilex™ 3 universal virtual platform is based on the Agilex™ 5 universal virtual platform. The descriptions of the Agilex™ 5 universal virtual platform apply to the Agilex™ 3 Universal Virtual Platform with the following exceptions:
  • The Agilex™ 3 universal virtual platform is associates with the agilex3c-universal.simics target script.
  • The HPS model in the Agilex™ 3 universal virtual platform is based on the Agilex™ 5 HPS model with a specific configuration to mimic the Agilex™ 3 device:
    • For the Agilex™ 3 HPS model, the version of the HPS Agilex™ 5 model (that is, features supported) is set as the production version of the device (B0 stepping).
    • For the Agilex™ 3 HPS model, only the A55 cores from the Agilex™ 5 HPS model are enabled, so you can use only Core 0 as a boot core.
    • For the Agilex™ 3 HPS model, the maximum core frequency from the Agilex™ 5 HPS model is limited to 800 MHz.

    These differences are handled as part of the target script. Be careful when using user-configurable parameters as these may be restricted to certain sets of values or even be ignored. For more information, refer to Agilex 5 Universal Virtual Platform User-Configurable Parameters.