Intel® Simics® Simulator for Altera® FPGAs: Agilex™ 5 and Agilex™ 3 Virtual Platform User Guide
ID
786901
Date
9/29/2025
Public
1. About This Document
2. Agilex™ 5/ Agilex™ 3 Intel® Simics® Virtual Platforms
3. Agilex™ 5/ Agilex™ 3 Universal Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5/ Agilex™ 3 HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History for Intel Simics Simulator for Altera FPGAs Agilex™ 5/ Agilex™ 3 Virtual Platform User Guide
2.1.1. Agilex™ 5 Universal Virtual Platform Overview
2.1.2. Agilex™ 3 Universal Virtual Platform Overview
2.1.3. Agilex™ 5 Universal Virtual Platform User-Configurable Parameters
2.1.4. Agilex™ 3 Universal Virtual Platform User-Configurable Parameters
2.1.5. Universal Virtual Platforms Key Capabilities
2.1.5.1. Boot-To-Operating System Prompt
2.1.5.2. Basic Ethernet
2.1.5.3. CPU Power-On and Boot Core Selection ( Agilex™ 5 only)
2.1.5.4. Reset Flow
2.1.5.5. General Purpose I/O (GPIO) Loopback
2.1.5.6. USB Disks Hot-Plug Support
2.1.5.7. On-Chip Memory IP FPGA Fabric Example Design
2.1.5.8. FPGA-to-HPS Bridges
2.1.5.9. Exercising Peripheral Subsystem in FPGA Fabric Design
2.1.5.10. USB Controller Host/Device Mode Configuration
2.1.5.11. HPS Component and Stepping Silicon Features Selection
2.1.5.12. UART1/UART2 Serial Console Selection
2.1.2. Agilex™ 3 Universal Virtual Platform Overview
The Agilex™ 3 universal virtual platform is based on the Agilex™ 5 universal virtual platform. The descriptions of the Agilex™ 5 universal virtual platform apply to the Agilex™ 3 Universal Virtual Platform with the following exceptions:
- The Agilex™ 3 universal virtual platform is associates with the agilex3c-universal.simics target script.
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The HPS model in the Agilex™ 3 universal virtual platform is based on the Agilex™ 5 HPS model with a specific configuration to mimic the Agilex™ 3 device:
- For the Agilex™ 3 HPS model, the version of the HPS Agilex™ 5 model (that is, features supported) is set as the production version of the device (B0 stepping).
- For the Agilex™ 3 HPS model, only the A55 cores from the Agilex™ 5 HPS model are enabled, so you can use only Core 0 as a boot core.
- For the Agilex™ 3 HPS model, the maximum core frequency from the Agilex™ 5 HPS model is limited to 800 MHz.
These differences are handled as part of the target script. Be careful when using user-configurable parameters as these may be restricted to certain sets of values or even be ignored. For more information, refer to Agilex 5 Universal Virtual Platform User-Configurable Parameters.