Intel® Simics® Simulator for Altera® FPGAs: Agilex™ 5 and Agilex™ 3 Virtual Platform User Guide
ID
786901
Date
9/29/2025
Public
1. About This Document
2. Agilex™ 5/ Agilex™ 3 Intel® Simics® Virtual Platforms
3. Agilex™ 5/ Agilex™ 3 Universal Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5/ Agilex™ 3 HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History for Intel Simics Simulator for Altera FPGAs Agilex™ 5/ Agilex™ 3 Virtual Platform User Guide
2.1.1. Agilex™ 5 Universal Virtual Platform Overview
2.1.2. Agilex™ 3 Universal Virtual Platform Overview
2.1.3. Agilex™ 5 Universal Virtual Platform User-Configurable Parameters
2.1.4. Agilex™ 3 Universal Virtual Platform User-Configurable Parameters
2.1.5. Universal Virtual Platforms Key Capabilities
2.1.5.1. Boot-To-Operating System Prompt
2.1.5.2. Basic Ethernet
2.1.5.3. CPU Power-On and Boot Core Selection ( Agilex™ 5 only)
2.1.5.4. Reset Flow
2.1.5.5. General Purpose I/O (GPIO) Loopback
2.1.5.6. USB Disks Hot-Plug Support
2.1.5.7. On-Chip Memory IP FPGA Fabric Example Design
2.1.5.8. FPGA-to-HPS Bridges
2.1.5.9. Exercising Peripheral Subsystem in FPGA Fabric Design
2.1.5.10. USB Controller Host/Device Mode Configuration
2.1.5.11. HPS Component and Stepping Silicon Features Selection
2.1.5.12. UART1/UART2 Serial Console Selection
2.1.5.5. General Purpose I/O (GPIO) Loopback
The Agilex™ 5 Universal Virtual Platform and Agilex™ 3 Universal Virtual Platform support a model that creates a loopback connection in certain pins in GPIO0 and GPIO1 ports. This feature is implemented at board component level.
The loopback implementation consists of directly connecting GPIO in and out pins of the GPIO ports in both directions to reflect the same state on those pins.
In each GPIO port, the following pairs of pins are connected as shown in the image below:
- [0,1]
- [5,6]
- [18,19]
- [20,21]
Figure 8. General Purpose I/O (GPIO) Loopback