Intel® Simics® Simulator for Altera® FPGAs: Agilex™ 5 and Agilex™ 3 Virtual Platform User Guide
                    
                        ID
                        786901
                    
                
                
                    Date
                    9/29/2025
                
                
                    Public
                
            
                
                    
                        1. About This Document
                    
                    
                
                    
                        2. Agilex™ 5/ Agilex™ 3 Intel® Simics® Virtual Platforms
                    
                    
                
                    
                        3. Agilex™ 5/ Agilex™ 3 Universal Virtual Platform Component Intel® Simics® Models
                    
                    
                
                    
                        4. Running a Simulation with the Agilex™ 5/ Agilex™ 3 HPS Model
                    
                    
                
                    
                    
                        5. Supported Use Cases
                    
                
                    
                    
                        6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
                    
                
                    
                    
                        A. Document Revision History for Intel Simics Simulator for Altera FPGAs Agilex™ 5/ Agilex™ 3 Virtual Platform User Guide
                    
                
            
        
                                    
                                    
                                        
                                            2.1.1. Agilex™ 5 Universal Virtual Platform Overview
                                        
                                        
                                        
                                    
                                        
                                        
                                            2.1.2. Agilex™ 3 Universal Virtual Platform Overview
                                        
                                        
                                    
                                        
                                        
                                            2.1.3. Agilex™ 5 Universal Virtual Platform User-Configurable Parameters
                                        
                                        
                                    
                                        
                                        
                                            2.1.4. Agilex™ 3 Universal Virtual Platform User-Configurable Parameters
                                        
                                        
                                    
                                        
                                            2.1.5. Universal Virtual Platforms Key Capabilities
                                        
                                        
                                        
                                    
                                
                            
                                                
                                                
                                                    
                                                    
                                                        2.1.5.1. Boot-To-Operating System Prompt
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.2. Basic Ethernet
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.3. CPU Power-On and Boot Core Selection ( Agilex™ 5 only)
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.4. Reset Flow
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.5. General Purpose I/O (GPIO) Loopback
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.6. USB Disks Hot-Plug Support
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.7. On-Chip Memory IP FPGA Fabric Example Design
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.8. FPGA-to-HPS Bridges
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.9. Exercising Peripheral Subsystem in FPGA Fabric Design
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.10. USB Controller Host/Device Mode Configuration
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.11. HPS Component and Stepping Silicon Features Selection
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.12. UART1/UART2 Serial Console Selection
                                                    
                                                    
                                                
                                            
                                        1.1. Terminology
This document uses the following terms:
| Term | Description | 
|---|---|
| eSW | Embedded software that runs on a virtual platform. | 
| Target script | Top-level .simics script in a virtual platform. This script defines the configuration parameters, run time commands, instantiation of the hardware model components, and any network configuration. | 
| Host PC | A computer on which the Intel® Simics® simulator runs. The Intel® Simics® host system is sometimes referred to as "host" or "host machine." | 
| Model | A model corresponds to a single building block within an Intel® Simics® virtual platform. Typically, an Intel® Simics® FPGA model aligns with an instance of an Altera® FPGA IP or a discrete board-level component such as a flash device. A virtual platform is created by instantiating models and connecting them together. | 
| Skeleton model | A type of Intel® Simics® model that includes the component interfaces and access to component registers with read/write supporting bit field restrictions and reset values. There are no side effects to reading/writing to registers. | 
| Target system | This is the physical hardware that the virtual platform simulates. A target system is sometimes referred to as a "target machine". | 
| Virtual platform | A virtual platform represents a target system that runs in an Intel® Simics® simulation environment. A virtual platform typically includes a processor model and any peripheral devices the processor accesses. |