Intel® Simics® Simulator for Altera® FPGAs: Agilex™ 5 and Agilex™ 3 Virtual Platform User Guide
                    
                        ID
                        786901
                    
                
                
                    Date
                    9/29/2025
                
                
                    Public
                
            
                
                    
                        1. About This Document
                    
                    
                
                    
                        2. Agilex™ 5/ Agilex™ 3 Intel® Simics® Virtual Platforms
                    
                    
                
                    
                        3. Agilex™ 5/ Agilex™ 3 Universal Virtual Platform Component Intel® Simics® Models
                    
                    
                
                    
                        4. Running a Simulation with the Agilex™ 5/ Agilex™ 3 HPS Model
                    
                    
                
                    
                    
                        5. Supported Use Cases
                    
                
                    
                    
                        6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
                    
                
                    
                    
                        A. Document Revision History for Intel Simics Simulator for Altera FPGAs Agilex™ 5/ Agilex™ 3 Virtual Platform User Guide
                    
                
            
        
                                    
                                    
                                        
                                            2.1.1. Agilex™ 5 Universal Virtual Platform Overview
                                        
                                        
                                        
                                    
                                        
                                        
                                            2.1.2. Agilex™ 3 Universal Virtual Platform Overview
                                        
                                        
                                    
                                        
                                        
                                            2.1.3. Agilex™ 5 Universal Virtual Platform User-Configurable Parameters
                                        
                                        
                                    
                                        
                                        
                                            2.1.4. Agilex™ 3 Universal Virtual Platform User-Configurable Parameters
                                        
                                        
                                    
                                        
                                            2.1.5. Universal Virtual Platforms Key Capabilities
                                        
                                        
                                        
                                    
                                
                            
                                                
                                                
                                                    
                                                    
                                                        2.1.5.1. Boot-To-Operating System Prompt
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.2. Basic Ethernet
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.3. CPU Power-On and Boot Core Selection ( Agilex™ 5 only)
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.4. Reset Flow
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.5. General Purpose I/O (GPIO) Loopback
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.6. USB Disks Hot-Plug Support
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.7. On-Chip Memory IP FPGA Fabric Example Design
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.8. FPGA-to-HPS Bridges
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.9. Exercising Peripheral Subsystem in FPGA Fabric Design
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.10. USB Controller Host/Device Mode Configuration
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.11. HPS Component and Stepping Silicon Features Selection
                                                    
                                                    
                                                
                                                    
                                                    
                                                        2.1.5.12. UART1/UART2 Serial Console Selection
                                                    
                                                    
                                                
                                            
                                        2.1.5.1. Boot-To-Operating System Prompt
The Agilex™ 5 Universal Virtual Platform and Agilex™ 3 Universal Virtual Platform allow exercising the HPS software in all parts of the boot flow for Linux* and Zephyr* operating systems. It provides the Intel® Simics® model of all hardware components needed for the boot flow.
- The exercised boot flow for Linux* operating systems goes from U-Boot SPL (FSBL) to Linux prompt passing through ATF and U-Boot (SSBL).
- The exercised boot flow for Zephyr* operating systems goes from ATF to Zephyr*, which immediately launches the application to run.
You can exercise the boot flow from a flash device such as an SD Card, NAND flash, or QSPI flash. Booting from an SD Card is the default boot mode.
For this capability, the following user-configurable parameters from the target script are used:
- Boot from SD Card: create_hps_sd_card = TRUE, fsbl_image_filename and sd_image_filename.
- Boot from NAND: create_hps_sd_card = FALSE, fsbl_image_filename, nand_data_image_filename and nand_spare_image_filename.
- Boot from QSPI: create_hps_sd_card = FALSE, fsbl_image_filename and qspi_image_filename.