Intel® Simics® Simulator for Altera® FPGAs: Agilex™ 5 and Agilex™ 3 Virtual Platform User Guide
ID
786901
Date
9/29/2025
Public
1. About This Document
2. Agilex™ 5/ Agilex™ 3 Intel® Simics® Virtual Platforms
3. Agilex™ 5/ Agilex™ 3 Universal Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5/ Agilex™ 3 HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History for Intel Simics Simulator for Altera FPGAs Agilex™ 5/ Agilex™ 3 Virtual Platform User Guide
2.1.1. Agilex™ 5 Universal Virtual Platform Overview
2.1.2. Agilex™ 3 Universal Virtual Platform Overview
2.1.3. Agilex™ 5 Universal Virtual Platform User-Configurable Parameters
2.1.4. Agilex™ 3 Universal Virtual Platform User-Configurable Parameters
2.1.5. Universal Virtual Platforms Key Capabilities
2.1.5.1. Boot-To-Operating System Prompt
2.1.5.2. Basic Ethernet
2.1.5.3. CPU Power-On and Boot Core Selection ( Agilex™ 5 only)
2.1.5.4. Reset Flow
2.1.5.5. General Purpose I/O (GPIO) Loopback
2.1.5.6. USB Disks Hot-Plug Support
2.1.5.7. On-Chip Memory IP FPGA Fabric Example Design
2.1.5.8. FPGA-to-HPS Bridges
2.1.5.9. Exercising Peripheral Subsystem in FPGA Fabric Design
2.1.5.10. USB Controller Host/Device Mode Configuration
2.1.5.11. HPS Component and Stepping Silicon Features Selection
2.1.5.12. UART1/UART2 Serial Console Selection
3.1.6. Agilex™ 5 B0 Features Support
The Agilex™ 5 Simics model offers the flexibility of supporting the A0 or B0 silicon stepping features. The selection of the stepping features is controlled through a parameter in the virtual platform target script in which the device is instantiated.
Remember: The Agilex™ 3 Simics model only supports the Agilex™ 5 B0 silicon stepping features. You can cannot modify the stepping for the Agilex™ 3 model.
The features described in this document apply to both A0 and B0 steppings, and only the following apply to the B0 stepping:
- Power management ability to bring up a secondary core by the HPS. This feature implements the PWRCTL_WRT_LOCK register that SDM sets during the boot core bring-up to prevent writing some power manager control registers, but still allow to set the PCHCTLR[TRIGGER_PCH_CPU] bits that allow releasing from reset the secondary cores.
- Reset controller ability to reset a secondary core from the boot core individually.
Note: To determine which stepping applies for the Agilex 5 E-Series device and the Agilex 5 D-Series device, refer to Agilex 5 HPS Component and Stepping Silicon Features Selection.