Intel® Simics® Simulator for Altera® FPGAs: Agilex™ 5 and Agilex™ 3 Virtual Platform User Guide

ID 786901
Date 9/29/2025
Public
Document Table of Contents

3.1.6. Agilex™ 5 B0 Features Support

The Agilex™ 5 Simics model offers the flexibility of supporting the A0 or B0 silicon stepping features. The selection of the stepping features is controlled through a parameter in the virtual platform target script in which the device is instantiated.

Remember: The Agilex™ 3 Simics model only supports the Agilex™ 5 B0 silicon stepping features. You can cannot modify the stepping for the Agilex™ 3 model.
The features described in this document apply to both A0 and B0 steppings, and only the following apply to the B0 stepping:
  • Power management ability to bring up a secondary core by the HPS. This feature implements the PWRCTL_WRT_LOCK register that SDM sets during the boot core bring-up to prevent writing some power manager control registers, but still allow to set the PCHCTLR[TRIGGER_PCH_CPU] bits that allow releasing from reset the secondary cores.
  • Reset controller ability to reset a secondary core from the boot core individually.
Note: To determine which stepping applies for the Agilex 5 E-Series device and the Agilex 5 D-Series device, refer to Agilex 5 HPS Component and Stepping Silicon Features Selection.