Intel® Simics® Simulator for Altera® FPGAs: Agilex™ 5 and Agilex™ 3 Virtual Platform User Guide

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ID 786901
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Agilex™ 5/ Agilex™ 3 Intel® Simics® Virtual Platforms 3. Agilex™ 5/ Agilex™ 3 Universal Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Agilex™ 5/ Agilex™ 3 HPS Model 5. Supported Use Cases 6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware A. Document Revision History for Intel Simics Simulator for Altera FPGAs Agilex™ 5/ Agilex™ 3 Virtual Platform User Guide
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Agilex™ 5/ Agilex™ 3 Intel® Simics® Virtual Platforms x
2.1. Agilex™ 5/ Agilex™ 3 Universal Virtual Platform
2.1. Agilex™ 5/ Agilex™ 3 Universal Virtual Platform x
2.1.1. Agilex™ 5 Universal Virtual Platform Overview 2.1.2. Agilex™ 3 Universal Virtual Platform Overview 2.1.3. Agilex™ 5 Universal Virtual Platform User-Configurable Parameters 2.1.4. Agilex™ 3 Universal Virtual Platform User-Configurable Parameters 2.1.5. Universal Virtual Platforms Key Capabilities
2.1.1. Agilex™ 5 Universal Virtual Platform Overview x
2.1.1.1. Agilex™ 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.5. Universal Virtual Platforms Key Capabilities x
2.1.5.1. Boot-To-Operating System Prompt 2.1.5.2. Basic Ethernet 2.1.5.3. CPU Power-On and Boot Core Selection ( Agilex™ 5 only) 2.1.5.4. Reset Flow 2.1.5.5. General Purpose I/O (GPIO) Loopback 2.1.5.6. USB Disks Hot-Plug Support 2.1.5.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.5.8. FPGA-to-HPS Bridges 2.1.5.9. Exercising Peripheral Subsystem in FPGA Fabric Design 2.1.5.10. USB Controller Host/Device Mode Configuration 2.1.5.11. HPS Component and Stepping Silicon Features Selection 2.1.5.12. UART1/UART2 Serial Console Selection
3. Agilex™ 5/ Agilex™ 3 Universal Virtual Platform Component Intel® Simics® Models x
3.1. HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components 3.5. Modeling Support Limitations
3.1. HPS Intel® Simics® Model x
3.1.1. Agilex™ 5/ Agilex™ 3 HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Agilex™ 5/ Agilex™ 3 HPS Components 3.1.6. Agilex™ 5 B0 Features Support
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card Device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Agilex™ 5/ Agilex™ 3 HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Agilex™ 5 or Agilex™ 3 Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Agilex™ 5/ Agilex™ 3 Intel® Simics® Virtual Platforms
3. Agilex™ 5/ Agilex™ 3 Universal Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5/ Agilex™ 3 HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History for Intel Simics Simulator for Altera FPGAs Agilex™ 5/ Agilex™ 3 Virtual Platform User Guide

1.2. List of Acronyms

Table 2.  Acronyms

Acronym

Term
ATF Arm* Trusted Firmware
CCU Cache Coherency Unit
CLI Command-line Interface
CPU Central Processing Unit
DHCP Dynamic Host Configuration Protocol
DRD Dual Role Device
EMIF External Memory Interfaces
EST Enhancements to Scheduled Traffic
eSW Embedded Software. Referred also as HPS Software.
FPE Frame Preemption
FPGA Field Programmable Gate Array
FSBL First Stage Bootloader
FSM Finite State Machine
GHRD Golden Hardware Reference Design
GSRD Golden System Reference Design
GPIO General Purpose I/O
HPS Hard Processor System
HS High Speed
ICMP Internet Control Message Protocol
IP Intellectual Property
JFFS2 Journaling Flash File System version 2
MAC Media Access Controller
MPFE Multi-port Front End
MPU Microprocessor Unit
NAPT Network Address Port Translation
OCRAM On-chip RAM
OTP One-time Programmable
OTG On-the-go
QSPI Quad Serial Peripheral Interface
RAM Random-access Memory
RTOS Real-time Operating System
SDM Security Device Manager
SCP Secure Copy Protocol
SCSI Small Computer System Interface
SMP Symmetric Multiprocessing
SPL Secondary Program Bootloader
SS Super Speed
TCP Transmission Control Protocol
TFTP Trivial File Transfer Protocol
TSN Time-sensitive Networking
UBIFS Unsorted Block Images File System
UDP User Datagram Protocol
USB Universal Serial Bus
VP Virtual Platform
XIP Execute in Place
Level Two Title