Intel® Simics® Simulator for Intel® FPGAs: Intel Agilex® 5 E-Series Virtual Platform User Guide

Download PDF
ID 786901
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About This Document 2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platform 3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model 5. Supported Use Cases A. Document Revision History
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platform x
2.1. Intel Agilex® 5 E-Series Universal Virtual Platform Overview 2.2. Intel Agilex® 5 E-Series Universal Virtual Platform User-Configurable Parameters 2.3. Intel Agilex® 5 E-Series Virtual Platform Key Capabilities 2.4. On-Chip Memory IP FPGA Fabric Example Design
2.1. Intel Agilex® 5 E-Series Universal Virtual Platform Overview x
2.1.1. Intel Agilex® 5 HPS Component 2.1.2. HPS Subsystem Component 2.1.3. FPGA Fabric Design 2.1.4. qsys_top Component 2.1.5. FPGA Component 2.1.6. Board Component 2.1.7. System Component 2.1.8. Target Script
2.3. Intel Agilex® 5 E-Series Virtual Platform Key Capabilities x
2.3.1. Boot-To-Operating System Prompt 2.3.2. Basic Ethernet 2.3.3. CPU Power-On and Boot Core Selection 2.3.4. Reset Flow 2.3.5. General Purpose I/O (GPIO) Loopback 2.3.6. USB Disks Hot-Plug Support
3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models x
3.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components
3.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model x
3.1.1. Intel Agilex® 5 E-Series HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Intel Agilex® 5 E-Series HPS Components
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Intel Agilex® 5 E-Series Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Intel Agilex® 5 E-Series Intel® Simics® Virtual Platform
3. Intel Agilex® 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Intel Agilex® 5 E-Series HPS Model
5. Supported Use Cases
A. Document Revision History

A. Document Revision History

Document Version Intel® Simics® Simulator for Intel® FPGAs Version Changes
2023.10.02 23.3
  • Rebranded all occurrences of "Simics" as "Intel Simics."
  • Made several editorial fixes in all topics.
  • Fixed branding errors of some third-party products.
  • Fixed formatting issues in several topics.
  • Updated List of Acronyms.
  • Updated the list of components and their descriptions in Intel Agilex 5 E-Series Intel Simics Virtual Platform.
  • Updated the image in Intel Agilex 5 E-Series Universal Virtual Platform Overview.
  • Enhanced the description and added SPI Controller functional block in Intel Agilex 5 E-Series Universal Virtual Platform Overview.
  • Enhanced the description and block diagram in FPGA Component and Board Component.
  • Added HPS component to Target Script.
  • Added additional parameters to Intel Agilex 5 E-Series Universal Virtual Platform User- Configurable Parameters.
  • Added a note and updated the parameters in Boot-To-Operating System Prompt.
  • Revised the information in Intel Agilex 5 HPS Component.
  • Revised the topic title of FPGA Fabric Example Design to On-Chip Memory IP FPGA Fabric Example Design.
  • Enhanced the information in Reset Flow and FPGA Fabric Example Design.
  • Updated the HPS subsystems image in Intel Agilex® 5 E-Series HPS Intel® Simics® Model Architecture
  • Updated the limitation and object names in PSS Subsystem Components
  • Updated the object names in MPU and APS Subsystem, MPFE Subsystem, Additional Intel Agilex 5 E-Series HPS Components, and External Memory Interface (EMIF).
  • Renamed the topic title "Virtual Platform FPGA Components" to "Virtual Platform HPS Subsystem Components."
  • Updated the components, limitations, and object names in Security Device Manager (SDM).
  • Renamed the topic title "QSPI Flash Device" to "SPI Flash Device."
  • Updated all the command outputs in Getting Device Information from the Intel Simics Model.
  • Added an image in General Purpose I/O (GPIO) Loopback.
  • Added the following new topics:
    • HPS Subsystem Component
    • FPGA Fabric Design
    • qsys_top Component
    • Virtual Platform qsys_top Components
    • FPGA Fabric
    • Intel® Simics® Text Console
2023.06.26 23.2
  • Updated "HPS Component".
  • Updated "Board Component"
  • Updated "User Configurable Parameters"
  • Added the following sections for new virtual platform board components:
    • "AT24Cxx EEPRom Device"
    • "I3C Device"
    • "USB Disk Device"
  • Updated block diagrams in the following topics:
    • " Intel Agilex® 5 E-Series Universal Virtual Platform Overview"
    • "FPGA Component"
    • "Board Component"
2024.04.03 23.1
  • Initial release
Level Two Title