High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

ID 773266
Date 12/04/2023

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3.2. Use Cases

This section explains the use cases that the HBM2E IP design example supports.

The HBM2E design example demonstrates two configurations for initiator-to-target NoC mapping: 1 x 1 full address connection, and 16 x 16 full crossbar. You can enable either of these configurations with AXI4-Lite and/or Fabric NoC.

The following table summarizes the supported configurations.

Table 2.  Supported Configurations
NoC Connectivity With Fabric NoC Fabric NoC with Dedicated AXI4-Lite NoC Initiator AXI4-Lite Support
Dedicated AXI4-Lite NoC Initiator Shared NoC Initiator for AXI4 and AXI4-Lite
1 x 1 Full Address Connection Supported Supported Supported Supported
16 x 16 Full Crossbar Supported Supported Supported Supported
Note: You can only configure the design example with a shared NoC initiator for AXI4-Lite and memory traffic when the NoC initiators and HBM2E channels are all configured in a 256-bit wide data mode.