High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

ID 773266
Date 12/04/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide

An automated design example flow is available for the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP. The HBM2E IP can generate design example file sets for synthesis and simulation.

You can use the Example Design tab and the Generate Example Design button in the HBM2E Intel FPGA IP IP Parameter Editor window to specify and generate synthesis and simulation example design file sets with which you can validate your HBM2E IP.

The generated design example reflects the parameterization that you set in the IP Parameter Editor window.

Intel provides a simulation and compilation-only design example that you can use to see the functionality of the IP and estimate the IP core area.

Note: The design example includes all needed NoC components; however, the abstract NoC model used in simulation does not reflect the true HBM2E throughput of Intel Agilex® 7 M-Series devices.
Figure 1. General Design Example Flow