High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

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ID 773266
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide 2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide 3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description 4. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example User Guide
1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide x
1.1. Release Information
2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide x
2.1. Creating an Intel® Quartus® Prime Project for Your HBM2E System 2.2. Configuring the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP 2.3. Generating the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example for Synthesis and Simulation 2.4. Compiling and Programming the Intel Agilex® 7 M-Series High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example 2.5. Using the HBM2E Design Example with the Test Engine IP 2.6. Enabling and Using the HBM2E Design Example with the Performance Monitor 2.7. Using the AXI4-Lite-enabled HBM2E Design Example in Hardware and Simulation 2.8. Simulating the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
2.8. Simulating the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x
2.8.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Example Design For Simulation 2.8.2. Simulating High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP with Synopsys VCS* 2.8.3. Simulating the HBM2E Intel FPGA IP with ModelSim SE 2.8.4. Simulating the HBM2E Intel FPGA IP with Cadence* Xcelium Parallel Simulator 2.8.5. Simulating High Bandwidth Memory (HBM2E) Interface IP Instantiated in Your Project
3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description x
3.1. Design Example Components 3.2. Use Cases 3.3. Top-Level Signals of the HBM2E Design Example 3.4. Using the HBM2E Design Example for Performance Testing
3.2. Use Cases x
3.2.1. Initiator to Target NoC Mapping 3.2.2. Fabric NoC 3.2.3. AXI4-Lite Support Dedicated AXI4-Lite NoC Initiator Shared NoC Initiator for AXI4 and AXI4-Lite
1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide
2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide
3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description
4. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example User Guide

3.2.3. AXI4-Lite Support

This topic details AXI4-Lite support.

Dedicated AXI4-Lite NoC Initiator

The HBM2E IP design example provides an option to enable AXI4-Lite for side-band traffic. As mentioned in the preceding table, you can choose AXI4-Lite support for any of the NoC configurations. You can also enable the fabric NoC with the AXI4-Lite in the same design example. Select Dedicated AXI-4 Lite NoC Initiator to enable AXI4-Lite access which is compatible with the fabric NoC option of the Design Example.

Note: You cannot enable fabric NoC with the Shared NoC initiator for AXI4 and AXI4-Lite feature of AXI4-Lite.
The following figure demonstrates how the NoC initiator IP is configured to enable:
  • Fabric NoC with dedicated AXI4-Lite.
  • AXI4-Lite only.
Figure 10. Dedicated AXI4-Lite NoC Initiator

There are two instances of the NoC initiator IP: One instance of the NoC initiator IP instantiates 2n initiators, where n is the number of channels enabled. If you enable the AXI4-Lite CSR access with a dedicated AXI4-Lite NoC initiator, the HBM2E design example instantiates another instance of the NoC initiator IP with a single initiator that is used for AXI4-Lite traffic.

This configuration can be used whether the fabric NoC is used to create wider data paths or not.

The following table summarizes which options to enable to select different configurations of the HBM2E design example.

Table 4.  HBM2E Configurations with Dedicated NoC Initiator for AXI4-Lite
Supported Configurations HBM2E IP Example Design Tab Options
Use Fabric NoC AXI4-Lite Support
Dedicated AXI4-Lite NoC Initiator Shared NoC Initiator for AXI4 and AXI4-Lite
Fabric NoC with AXI4-Lite Enabled Enabled Disabled
AXI4-Lite (no initiator sharing) Disabled Enabled Disabled

Shared NoC Initiator for AXI4 and AXI4-Lite

The HBM2E design example offers an option to share the initiator with either AXI main-band traffic or AXI4-Lite sideband traffic, when there is no available initiator that can be dedicated to AXI4-Lite traffic. Select Shared NoC Initiator for AXI4 and AXI4-Lite to enable this feature.

Table 5.  HBM2E Configurations with Shared NoC Initiator
Supported Configurations HBM2E IP Example Design Tab Options
Use Fabric NoC AXI4-Lite Support
Dedicated AXI4-Lite NoC Initiator Shared NoC Initiator for AXI4 and AXI4-Lite
With AXI4-Lite (with initiator sharing) Not Supported Disabled Enabled
Figure 11. Shared NoC Initiator for AXI4 and AXI4-Lite

As the above figure shows, this option instantiates four instances of the NoC initiator IP, each exposing one AXI4-Lite interface and multiple AXI4-mainband interfaces, which depends on the number of channels enabled. The above diagram illustrates the example where all 8 channels are enabled. The AXI4-Lite interface and one of the AXI4 interfaces are multiplexed so that AXI4 or AXI4-Lite traffic go through one initiator. Initiator sharing is not available with initiators that are configured to use the fabric NoC for read response data.

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