High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP User Guide

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ID 773264
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP User Guide 2. Introduction to High Bandwidth Memory 3. Agilex™ 7 M-Series HBM2E Architecture 4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP 5. High Bandwidth Memory (HBM2E) Interface FPGA IP Interface 6. High Bandwidth Memory (HBM2E) Interface FPGA IP Performance 7. Debugging the High Bandwidth Memory (HBM2E) Interface FPGA IP 8. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP User Guide A. High Bandwidth Memory (HBM2E) Interface FPGA IP Quartus® Prime Software Flow
1. About the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP User Guide x
1.1. Release Information
2. Introduction to High Bandwidth Memory x
2.1. HBM2E in Agilex™ 7 M-Series Devices 2.2. HBM2E DRAM Structure 2.3. Agilex™ 7 HBM2E Features 2.4. Agilex™ 7 M-Series HBM2E Controller Features 2.5. Agilex™ 7 M-Series FPGA HBM2E IP Device Family Support
3. Agilex™ 7 M-Series HBM2E Architecture x
3.1. Agilex™ 7 M-Series HBM2E Introduction 3.2. Agilex™ 7 M-Series Hard Memory NoC Subsystem 3.3. Address Mapping of the HBM2E Targets 3.4. Agilex™ 7 M-Series UIB Architecture 3.5. Agilex™ 7 M-Series HBM2E Controller Architecture
3.5. Agilex™ 7 M-Series HBM2E Controller Architecture x
3.5.1. Agilex™ 7 M-Series HBM2E Controller Details
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP x
4.1. Creating an Quartus® Prime Pro Edition Project for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP
4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP x
4.2.1. General Parameters for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2.2. Example Design Parameters for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2.3. Modifying Your Pin Assignments to Choose the Physical Location of the HBM2E Device
5. High Bandwidth Memory (HBM2E) Interface FPGA IP Interface x
5.1. High Bandwidth Memory (HBM2E) Interface FPGA IP High Level Block Diagram 5.2. High Bandwidth Memory (HBM2E) Interface FPGA IP Controller Interface Signals 5.3. User AXI Interface Timing 5.4. Platform Designer-Only Interface 5.5. User Accesses to the HBM2E Controller
5.2. High Bandwidth Memory (HBM2E) Interface FPGA IP Controller Interface Signals x
5.2.1. Reset, Clock, and Calibration Status Signals Clocking recommendations for Reliable Calibration of the HBM2E Interface 5.2.2. Requirement and Timing of the hbm_reset_n Signal 5.2.3. 'Do not connect' Signals 5.2.4. Asynchronous HBM2E Controller Signals 5.2.5. AXI4 Interface Signals 5.2.6. AXI4-Lite Interface
5.3. User AXI Interface Timing x
5.3.1. AXI Write Transaction 5.3.2. AXI Read Transaction
5.5. User Accesses to the HBM2E Controller x
5.5.1. Initialization Control Register and Initialization Status Register 5.5.2. Thermal Status Register 5.5.3. ECC Error Counters Register 5.5.4. Error Login Registers 5.5.5. Error Injection Registers
6. High Bandwidth Memory (HBM2E) Interface FPGA IP Performance x
6.1. High Bandwidth Memory (HBM2E) Interface FPGA IP Controller Performance 6.2. High Bandwidth Memory (HBM2E) Interface FPGA IP System Performance
6.1. High Bandwidth Memory (HBM2E) Interface FPGA IP Controller Performance x
6.1.1. High Bandwidth Memory (HBM2E) DRAM Bandwidth 6.1.2. High Bandwidth Memory (HBM2E) Interface FPGA IP Efficiency 6.1.3. High Bandwidth Memory (HBM2E) Interface FPGA IP Latency 6.1.4. High Bandwidth Memory (HBM2E) Interface FPGA IP Timing
7. Debugging the High Bandwidth Memory (HBM2E) Interface FPGA IP x
7.1. Debugging Guidelines for High Bandwidth Memory (HBM2E) Interface FPGA IP
A. High Bandwidth Memory (HBM2E) Interface FPGA IP Quartus® Prime Software Flow x
A.1. Initiators Placement Recommendations A.2. Simulating HBM2E User Designs
1. About the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP User Guide
2. Introduction to High Bandwidth Memory
3. Agilex™ 7 M-Series HBM2E Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP
5. High Bandwidth Memory (HBM2E) Interface FPGA IP Interface
6. High Bandwidth Memory (HBM2E) Interface FPGA IP Performance
7. Debugging the High Bandwidth Memory (HBM2E) Interface FPGA IP
8. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP User Guide
A. High Bandwidth Memory (HBM2E) Interface FPGA IP Quartus® Prime Software Flow

5.2.1. Reset, Clock, and Calibration Status Signals

Table 17.  Reset Signals
Signal Direction Description
hbm_reset_n Input User-initiated, negative-edge HBM reset coming from core fabric. Resets the UIB subsystem, including HBM controller, PHY, and HBM2E DRAM.
hbm_reset_in_prog Output When this signal is high, it indicates that the user-initiated HBM reset (hbm_reset_n) is in progress. Additional assertions of hbm_reset_n are ignored while hbm_reset_in_prog remains high.
Table 18.  Clock Signals
Signal Direction Description
uibpll_refclk Input Reference clock input for the UIB PLL. This clock must be stable and free-running at device power-up for successful configuration. Refer to Agilex™ 7 pin connection guidelines for information on how to supply this clock.
fabric_clk Input Core clock used to synchronize reset and status signals.
Table 19.  Calibration Status Signals
Signal Direction Description
local_cal_success Output Indicates calibration success. This signal is asynchronous. Once asserted, this signal remains high until an HBM reset with calibration is attempted.
local_cal_fail Output Indicates calibration failure. This signal is asynchronous. Once asserted, this signal remains high until an HBM reset with calibration is attempted.

Clocking recommendations for Reliable Calibration of the HBM2E Interface

Observe the following clock guidelines for reliable calibration of the HBM2E interface:

  • The UIB PLL reference clocks (one per HBM2E interface) must be provided through an external clock source and must be stable and free-running prior to configuration and stable thereafter.
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