Visible to Intel only — GUID: xaj1713308267921
Ixiasoft
Visible to Intel only — GUID: xaj1713308267921
Ixiasoft
5.5.5. Error Injection Registers
To read the error injection control registers, issue a read command to the register at the offset 32’h0600 for pseudo-channel 0 and 32’h0900 for the pseudo-channel 1.
Bits | Access | Default | Name | Description |
---|---|---|---|---|
[1:0] | RW | 2’b00 | R_INJ_ERR | 2’b00: No operation. 2’b01: Initiator injects errors just once for all selected errors through R_ERRINJ register. 2’b1x: Initiator injects errors, the count determined by R_INJ_CNT, for all selected errors through R_ERRINJ register. |
[4:2] | RW | 3’b000 | R_INJ_CNT | Indicates the count of error injected. Default indicates error injected for one transfer. 3’b111 means error injected for eight consecutive transfers. |
[31:5] | Reserved * | Reserved. | ||
* When bits are marked as reserved, it is essential that software treat these bits as set to zero. Any non-zero value written to the reserved bits may result in unexpected or undefined behavior. |
To read the error injection registers, issue a read command to the register at the offset 32’h0604 for pseudo-channel 0 and 32’h0904 for the pseudo-channel 1.
Bits | Access | Default | Name | Description |
---|---|---|---|---|
[0] | RW | 1’b0 | DRAM_SBE_INJ | Indicates single-bit Error (SBE) Injection on generated ECC in Responder. |
[1] | RW | 1’b0 | DRAM_DBE_INJ | Indicates double-bit Error (DBE) Injection on generated ECC in Responder. |
[16:2] | Reserved * | Reserved. | ||
[17]] | RW | 1’b0 | BRESP_BIT0_INJ | 1: Response bit is flipped on the interface. 0: Response bit is normal on the interface. |
[18] | RW | 1’b0 | BRESP_BIT1_INJ | 1: Response bit is flipped on the interface. 0: Response bit is normal on the interface. |
[24:19] | Reserved * | Reserved. | ||
[25] | RW | 1’b0 | RRESP_BIT0_INJ | 1: Response bit is flipped on the interface. 0: Response bit is normal on the interface. |
[26] | RW | 1’b0 | RRESP_BIT1_INJ | 1: Response bit is flipped on the interface. 0: Response bit is normal on the interface. |
[31:27] | Reserved * | Reserved. |