High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP User Guide

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ID 773264
Date 11/04/2024
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Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP User Guide 2. Introduction to High Bandwidth Memory 3. Agilex™ 7 M-Series HBM2E Architecture 4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP 5. High Bandwidth Memory (HBM2E) Interface FPGA IP Interface 6. High Bandwidth Memory (HBM2E) Interface FPGA IP Performance 7. Debugging the High Bandwidth Memory (HBM2E) Interface FPGA IP 8. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP User Guide A. High Bandwidth Memory (HBM2E) Interface FPGA IP Quartus® Prime Software Flow
1. About the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP User Guide x
1.1. Release Information
2. Introduction to High Bandwidth Memory x
2.1. HBM2E in Agilex™ 7 M-Series Devices 2.2. HBM2E DRAM Structure 2.3. Agilex™ 7 HBM2E Features 2.4. Agilex™ 7 M-Series HBM2E Controller Features 2.5. Agilex™ 7 M-Series FPGA HBM2E IP Device Family Support
3. Agilex™ 7 M-Series HBM2E Architecture x
3.1. Agilex™ 7 M-Series HBM2E Introduction 3.2. Agilex™ 7 M-Series Hard Memory NoC Subsystem 3.3. Address Mapping of the HBM2E Targets 3.4. Agilex™ 7 M-Series UIB Architecture 3.5. Agilex™ 7 M-Series HBM2E Controller Architecture
3.5. Agilex™ 7 M-Series HBM2E Controller Architecture x
3.5.1. Agilex™ 7 M-Series HBM2E Controller Details
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP x
4.1. Creating an Quartus® Prime Pro Edition Project for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP
4.2. Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP x
4.2.1. General Parameters for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2.2. Example Design Parameters for High Bandwidth Memory (HBM2E) Interface FPGA IP 4.2.3. Modifying Your Pin Assignments to Choose the Physical Location of the HBM2E Device
5. High Bandwidth Memory (HBM2E) Interface FPGA IP Interface x
5.1. High Bandwidth Memory (HBM2E) Interface FPGA IP High Level Block Diagram 5.2. High Bandwidth Memory (HBM2E) Interface FPGA IP Controller Interface Signals 5.3. User AXI Interface Timing 5.4. Platform Designer-Only Interface 5.5. User Accesses to the HBM2E Controller
5.2. High Bandwidth Memory (HBM2E) Interface FPGA IP Controller Interface Signals x
5.2.1. Reset, Clock, and Calibration Status Signals 5.2.2. Requirement and Timing of the hbm_reset_n Signal 5.2.3. 'Do not connect' Signals 5.2.4. Asynchronous HBM2E Controller Signals 5.2.5. AXI4 Interface Signals 5.2.6. AXI4-Lite Interface
5.3. User AXI Interface Timing x
5.3.1. AXI Write Transaction 5.3.2. AXI Read Transaction
5.5. User Accesses to the HBM2E Controller x
5.5.1. Initialization Control Register and Initialization Status Register 5.5.2. Thermal Status Register 5.5.3. ECC Error Counters Register 5.5.4. Error Login Registers 5.5.5. Error Injection Registers
6. High Bandwidth Memory (HBM2E) Interface FPGA IP Performance x
6.1. High Bandwidth Memory (HBM2E) Interface FPGA IP Controller Performance 6.2. High Bandwidth Memory (HBM2E) Interface FPGA IP System Performance
6.1. High Bandwidth Memory (HBM2E) Interface FPGA IP Controller Performance x
6.1.1. High Bandwidth Memory (HBM2E) DRAM Bandwidth 6.1.2. High Bandwidth Memory (HBM2E) Interface FPGA IP Efficiency 6.1.3. High Bandwidth Memory (HBM2E) Interface FPGA IP Latency 6.1.4. High Bandwidth Memory (HBM2E) Interface FPGA IP Timing
7. Debugging the High Bandwidth Memory (HBM2E) Interface FPGA IP x
7.1. Debugging Guidelines for High Bandwidth Memory (HBM2E) Interface FPGA IP
A. High Bandwidth Memory (HBM2E) Interface FPGA IP Quartus® Prime Software Flow x
A.1. Initiators Placement Recommendations A.2. Simulating HBM2E User Designs
1. About the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP User Guide
2. Introduction to High Bandwidth Memory
3. Agilex™ 7 M-Series HBM2E Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface FPGA IP
5. High Bandwidth Memory (HBM2E) Interface FPGA IP Interface
6. High Bandwidth Memory (HBM2E) Interface FPGA IP Performance
7. Debugging the High Bandwidth Memory (HBM2E) Interface FPGA IP
8. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP User Guide
A. High Bandwidth Memory (HBM2E) Interface FPGA IP Quartus® Prime Software Flow

5.5.4. Error Login Registers

These per-pseudo-channel registers log the first error on the read/write command. Error data is held by hardware until you clear the lock bit on the register.

To access the write register for Log 0, Log 1, Log 2, or Log 3, issue the read command to the offset 0x540h/0x544/0x548/0x54C for pseudo-channel 0 and 0x840/0x844/0x848/0x84C for pseudo-channel 1.

To access the read register for Log 0, Log 1, Log 2, or Log 3, issue the read command to the offset 0x550h/0x554/0x558/0x55C for pseudo-channel 0 and 0x850/0x854/0x858/0x85C for pseudo-channel 1.

Table 37.  Write Command Log 0 Register
Bits Access Default Name Description
14:0 RO 15'b0 AWID Write ID for the error transaction.
15 RO 1'b0 Reserved. Reserved.
23:16 RO 8'b0 AWLEN Write Burst length for the error transaction.
26:24 RO 3'b0 AWSIZE Write Burst size for the error transaction.
28:27 RO 2'b0 AWBURST Write Burst type for the error transaction.
29 RO 1'b0 AWLOCK Write Lock type for the error transaction.
31:30 RO 2'b0 Reserved. Reserved.

Table 38.  Write Command Log 1 Register
Bits Access Default Name Description
31:0 RO 32'b0 AWADDR_LO Lower 32-bits of write address for the error transaction.

Table 39.  Write Command Log 2 Register
Bits Access Default Name Description
31:0 RO 32'b0 AWADDR_HI Upper 32-bits of write address for the error transaction.

Table 40.  Write Command Log 3 Register
Bits Access Default Name Description
2:0 RO 3'b0 AWPROT Write protection type for the error transaction.
6:3 RO 4'b0 AWQOS Write QOS for the error transaction.
30:7 RO 24'b0 Reserved. Reserved.
31 RW1C 1'b0 R_AWHDRLOG_LOCK This bit is set when 0540h/0840h- 054Fh/084Fh registers are captured. Software write 1 to clears it.

Table 41.  Read Command Log 0 Register
Bits Access Default Name Description
14:0 RO 15'b0 ARID Read ID for the error transaction.
15 RO 1'b0 Reserved. Reserved.
23:16 RO 8'b0 ARLEN Read Burst length for the error transaction.
26:24 RO 3'b0 ARSIZE Read Burst size for the error transaction.
28:27 RO 2'b0 ARBURST Read Burst type for the error transaction.
29 RO 1'b0 ARLOCK Read Lock type for the error transaction.
31:30 RO 2'b0 Reserved. Reserved.

Table 42.  Read Command Log 1 Register
Bits Access Default Name Description
31:0 RO 32'b0 ARADDR_LO Lower 32-bits of read address for the error transaction.

Table 43.  Read Command Log 2 Register
Bits Access Default Name Description
31:0 RO 32'b0 ARADDR_HI Upper 32-bits of read Address for the error transaction.

Table 44.  Read Command Log 3 Register
Bits Access Default Name Description
2:0 RO 3'b0 ARPROT Read protection type for the error transaction.
6:3 RO 4'b0 ARQOS Read QOS for the error transaction.
30:7 RO 24'b0 Reserved. Reserved.
31 RW1C 1'b0 R_ARHDRLOG_LOCK This bit is set when 0550h/0850h- 055Fh/085Fh registers are captured. Software clears it.
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